Total properties:
67
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12115784
|
Filing Dt:
|
05/06/2008
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
Title:
|
POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12143285
|
Filing Dt:
|
06/20/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12166876
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
MULITPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12168354
|
Filing Dt:
|
07/07/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
DATA STORAGE AND STACKABLE CONFIGURATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12210580
|
Filing Dt:
|
09/15/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12211159
|
Filing Dt:
|
09/16/2008
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
Title:
|
CACHE FILTERING METHOD AND APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12258056
|
Filing Dt:
|
10/24/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
|
Application #:
|
12329929
|
Filing Dt:
|
12/08/2008
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12364665
|
Filing Dt:
|
02/03/2009
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
Title:
|
FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12401963
|
Filing Dt:
|
03/11/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12429310
|
Filing Dt:
|
04/24/2009
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12488278
|
Filing Dt:
|
06/19/2009
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12495089
|
Filing Dt:
|
06/30/2009
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12508926
|
Filing Dt:
|
07/24/2009
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
Title:
|
BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12533732
|
Filing Dt:
|
07/31/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12607680
|
Filing Dt:
|
10/28/2009
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
Title:
|
BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12757540
|
Filing Dt:
|
04/09/2010
|
Publication #:
|
|
Pub Dt:
|
03/03/2011
| | | | |
Title:
|
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12773340
|
Filing Dt:
|
05/04/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12816130
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12827718
|
Filing Dt:
|
06/30/2010
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12903271
|
Filing Dt:
|
10/13/2010
|
Publication #:
|
|
Pub Dt:
|
02/10/2011
| | | | |
Title:
|
POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
12967918
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13005774
|
Filing Dt:
|
01/13/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13038461
|
Filing Dt:
|
03/02/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13040324
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13042571
|
Filing Dt:
|
03/08/2011
|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
Title:
|
MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13073150
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13090427
|
Filing Dt:
|
04/20/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13091465
|
Filing Dt:
|
04/21/2011
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13094613
|
Filing Dt:
|
04/26/2011
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH CONFIGURABLE THROUGH-SILICON VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13094619
|
Filing Dt:
|
04/26/2011
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13110399
|
Filing Dt:
|
05/18/2011
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PHASE CHANGE MEMORY WORD LINE DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
13159060
|
Filing Dt:
|
06/13/2011
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13249744
|
Filing Dt:
|
09/30/2011
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13276856
|
Filing Dt:
|
10/19/2011
|
Publication #:
|
|
Pub Dt:
|
02/09/2012
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13348107
|
Filing Dt:
|
01/11/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13365895
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
13408252
|
Filing Dt:
|
02/29/2012
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13467491
|
Filing Dt:
|
05/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13592953
|
Filing Dt:
|
08/23/2012
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13617908
|
Filing Dt:
|
09/14/2012
|
Publication #:
|
|
Pub Dt:
|
01/10/2013
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER-SAVING FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13655582
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13713320
|
Filing Dt:
|
12/13/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13743899
|
Filing Dt:
|
01/17/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
13765059
|
Filing Dt:
|
02/12/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
DATA STORAGE AND STACKABLE CHIP CONFIGURATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13777485
|
Filing Dt:
|
02/26/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13777645
|
Filing Dt:
|
02/26/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13860724
|
Filing Dt:
|
04/11/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13912650
|
Filing Dt:
|
06/07/2013
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13951132
|
Filing Dt:
|
07/25/2013
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
Title:
|
MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13973600
|
Filing Dt:
|
08/22/2013
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
Title:
|
PHASE CHANGE MEMORY WORD LINE DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
14026359
|
Filing Dt:
|
09/13/2013
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
Title:
|
DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2018
|
Application #:
|
14027858
|
Filing Dt:
|
09/16/2013
|
Publication #:
|
|
Pub Dt:
|
01/16/2014
| | | | |
Title:
|
BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
14032816
|
Filing Dt:
|
09/20/2013
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
14082454
|
Filing Dt:
|
11/18/2013
|
Publication #:
|
|
Pub Dt:
|
03/13/2014
| | | | |
Title:
|
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2021
|
Application #:
|
14097506
|
Filing Dt:
|
12/05/2013
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
14101507
|
Filing Dt:
|
12/10/2013
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
14158116
|
Filing Dt:
|
01/17/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14254865
|
Filing Dt:
|
04/16/2014
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14268350
|
Filing Dt:
|
05/02/2014
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
|
Application #:
|
14625858
|
Filing Dt:
|
02/19/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14753500
|
Filing Dt:
|
06/29/2015
|
Publication #:
|
|
Pub Dt:
|
12/17/2015
| | | | |
Title:
|
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
14795114
|
Filing Dt:
|
07/09/2015
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
14809831
|
Filing Dt:
|
07/27/2015
|
Publication #:
|
|
Pub Dt:
|
01/07/2016
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
14886190
|
Filing Dt:
|
10/19/2015
|
Publication #:
|
|
Pub Dt:
|
04/07/2016
| | | | |
Title:
|
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
15266196
|
Filing Dt:
|
09/15/2016
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
MULTIPAGE PROGRAM SCHEME FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15411138
|
Filing Dt:
|
01/20/2017
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
|
|