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Patent #:
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Issue Dt:
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01/25/2011
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Application #:
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11552764
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Filing Dt:
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10/25/2006
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Publication #:
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Pub Dt:
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05/17/2007
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Title:
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METHOD AND APPARATUS FOR OVERFLOWING DATA PACKETS TO A SOFTWARE-CONTROLLED MEMORY WHEN THEY DO NOT FIT INTO A HARDWARE-CONTROLLED MEMORY
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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11557005
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Filing Dt:
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11/06/2006
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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EXTERNAL TRACE SYNCHRONIZATION VIA PERIODIC SAMPLING
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11566870
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Filing Dt:
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12/05/2006
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Publication #:
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Pub Dt:
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11/01/2007
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Title:
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CONTEXT SELECTION AND ACTIVATION MECHANISM FOR ACTIVATING ONE OF A GROUP OF INACTIVE CONTEXTS IN A PROCESSOR CORE FOR SERVICING INTERRUPTS
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11611064
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Filing Dt:
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12/14/2006
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Publication #:
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Pub Dt:
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04/19/2007
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Title:
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BARREL-INCREMENTER-BASED ROUND-ROBIN APPARATUS AND INSTRUCTION DISPATCH SCHEDULER EMPLOYING SAME FOR USE IN MULTITHREADING MICROPROCESSOR
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11616539
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Filing Dt:
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12/27/2006
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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EFFICIENT RESOURCE ARBITRATION
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Patent #:
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Issue Dt:
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11/23/2010
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Application #:
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11616558
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Filing Dt:
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12/27/2006
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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SPECULATIVE CACHE TAG EVALUATION
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Patent #:
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Issue Dt:
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02/09/2010
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Application #:
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11620362
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Filing Dt:
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01/05/2007
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Publication #:
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Pub Dt:
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05/17/2007
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Title:
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MULTITHREADING INSTRUCTION SCHEDULER EMPLOYING THREAD GROUP PRIORITIES
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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11627899
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Filing Dt:
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01/26/2007
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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SYSTEMS AND METHODS FOR CONTROLLING THE USE OF PROCESSING ALGORITHMS, AND APPLICATIONS THEREOF
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11636462
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Filing Dt:
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12/11/2006
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Publication #:
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Pub Dt:
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04/26/2007
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Title:
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SELECTION OF ISA DECODING MODE FOR PLURAL INSTRUCTION SETS BASED UPON INSTRUCTION ADDRESS
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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11640491
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Filing Dt:
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12/18/2006
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Publication #:
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Pub Dt:
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04/03/2008
| | | | |
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Title:
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CONDITIONAL MOVE INSTRUCTION FORMED INTO ONE DECODED INSTRUCTION TO BE GRADUATED AND ANOTHER DECODED INSTRUCTION TO BE INVALIDATED
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11644001
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Filing Dt:
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12/22/2006
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Publication #:
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Pub Dt:
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05/10/2007
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Title:
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VIRTUAL INSTRUCTION EXPANSION USING PARAMETER SELECTOR DEFINING LOGICAL OPERATION ON PARAMETERS FOR TEMPLATE OPCODE SUBSTITUTION
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Patent #:
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Issue Dt:
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02/03/2009
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Application #:
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11668582
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Filing Dt:
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01/30/2007
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Publication #:
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Pub Dt:
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05/31/2007
| | | | |
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Title:
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METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS
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Patent #:
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Issue Dt:
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04/13/2010
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Application #:
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11674924
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Filing Dt:
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02/14/2007
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Publication #:
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Pub Dt:
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08/16/2007
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Title:
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CONFIGURABLE CO-PROCESSOR INTERFACE
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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11676242
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Filing Dt:
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02/16/2007
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Publication #:
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Pub Dt:
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08/02/2007
| | | | |
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Title:
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TRACE CONTROL FROM HARDWARE AND SOFTWARE
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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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11676541
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Filing Dt:
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02/20/2007
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Publication #:
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Pub Dt:
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12/20/2007
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING ATOMICITY OF MEMORY OPERATIONS IN DYNAMIC MULTI-STREAMING PROCESSORS
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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11684156
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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SYSTEM AND METHOD FOR MANAGING THE DESIGN AND CONFIGURATION OF AN
INTEGRATED CIRCUIT SEMICONDUCTOR DESIGN
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11684189
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
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Title:
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Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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11684205
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
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Title:
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PROTECTING TRADE SECRETS DURING THE DESIGN AND CONFIGURATION OF AN INTEGRATED CIRCUIT SEMICONDUCTOR DESIGN
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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11702659
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Filing Dt:
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02/06/2007
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Publication #:
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Pub Dt:
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10/25/2007
| | | | |
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Title:
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ALIGNMENT AND ORDERING OF VECTOR ELEMENTS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSING
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11727640
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Filing Dt:
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03/27/2007
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Publication #:
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Pub Dt:
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10/11/2007
| | | | |
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Title:
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AN INSTRUCTION PROCESSOR HAVING MULTIPLE EXECUTION PIPELINES
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Patent #:
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Issue Dt:
|
02/08/2011
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Application #:
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11747666
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Filing Dt:
|
05/11/2007
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Publication #:
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Pub Dt:
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11/13/2008
| | | | |
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Title:
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SYSTEM DEBUG AND TRACE SYSTEM AND METHOD, AND APPLICATIONS THEREOF
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|
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Patent #:
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|
Issue Dt:
|
06/02/2009
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Application #:
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11764137
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Filing Dt:
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06/15/2007
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Publication #:
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Pub Dt:
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01/24/2008
| | | | |
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Title:
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FULL SCAN SOLUTION FOR LATCHED-BASED DESIGN
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/03/2010
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Application #:
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11767225
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
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Title:
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PREVENTING WRITEBACK RACE IN MULTIPLE CORE PROCESSORS
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Patent #:
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Issue Dt:
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08/03/2010
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Application #:
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11767261
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
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Title:
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AVOIDING LIVELOCK USING INTERVENTION MESSAGES IN MULTIPLE CORE PROCESSORS
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Patent #:
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Issue Dt:
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05/25/2010
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Application #:
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11806845
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Filing Dt:
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06/04/2007
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Publication #:
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Pub Dt:
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01/24/2008
| | | | |
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Title:
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PROCESSOR HAVING A COMPARE EXTENSION OF AN INSTRUCTION SET ARCHITECTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
11830795
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Filing Dt:
|
07/30/2007
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Publication #:
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Pub Dt:
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02/05/2009
| | | | |
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Title:
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APPARATUS AND METHOD FOR EVALUATING A FREE-RUNNING TRACE STREAM
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Patent #:
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|
Issue Dt:
|
11/29/2011
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Application #:
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11838648
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Filing Dt:
|
08/14/2007
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Publication #:
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Pub Dt:
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02/19/2009
| | | | |
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Title:
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POWER MANAGEMENT FOR SYSTEM HAVING ONE OR MORE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
03/06/2012
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Application #:
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11859198
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Filing Dt:
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09/21/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
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Title:
|
SUPPORT FOR MULTIPLE COHERENCE DOMAINS
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
|
11864363
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Filing Dt:
|
09/28/2007
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Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
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Title:
|
SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/15/2010
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Application #:
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11868429
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Filing Dt:
|
10/05/2007
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Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
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Title:
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INSTRUCTION ENCODING TO INDICATE WHETHER TO STORE ARGUMENT REGISTERS AS STATIC REGISTERS AND RETURN ADDRESS IN SUBROUTINE STACK
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/05/2009
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Application #:
|
11876442
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Filing Dt:
|
10/22/2007
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED COMPUTER LOAD AND STORE OPERATIONS
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11896424
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Filing Dt:
|
08/31/2007
|
|
Publication #:
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Pub Dt:
|
03/05/2009
| | | | |
|
Title:
|
Low-overhead/power-saving processor synchronization mechanism, and applications thereof
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/29/2012
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Application #:
|
11943751
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Filing Dt:
|
11/21/2007
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
|
Title:
|
RANDOM CACHE LINE REFILL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
11949418
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Filing Dt:
|
12/03/2007
|
|
Publication #:
|
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Pub Dt:
|
07/31/2008
| | | | |
|
Title:
|
PROCESSOR WITH IMPROVED ACCURACY FOR MULTIPLY-ADD OPERATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/29/2011
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Application #:
|
11963503
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Filing Dt:
|
12/21/2007
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Publication #:
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Pub Dt:
|
06/25/2009
| | | | |
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Title:
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APPARATUS AND METHOD FOR CONTROLLING THE EXCLUSIVITY MODE OF A LEVEL-TWO CACHE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/29/2011
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Application #:
|
11976713
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Filing Dt:
|
10/26/2007
|
|
Publication #:
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Pub Dt:
|
04/30/2009
| | | | |
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Title:
|
AUTOMATED DIGITAL CIRCUIT DESIGN TOOL THAT REDUCES OR ELIMINATES ADVERSE TIMING CONSTRAINTS DUE TO AN INHERENT CLOCK SIGNAL SKEW, AND APPLICATIONS THEREOF
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/01/2011
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Application #:
|
12000413
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Filing Dt:
|
12/12/2007
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|
Publication #:
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Pub Dt:
|
06/18/2009
| | | | |
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Title:
|
CLOCK RATIO CONTROLLER FOR DYNAMIC VOLTAGE AND FREQUENCY SCALED DIGITAL SYSTEMS, AND APPLICATIONS THEREOF
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/20/2011
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Application #:
|
12021110
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Filing Dt:
|
01/28/2008
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|
Publication #:
|
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Pub Dt:
|
07/30/2009
| | | | |
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Title:
|
VIRTUAL PROCESSOR BASED SECURITY FOR ON-CHIP MEMORY, AND APPLICATIONS THEREOF
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|
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Patent #:
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|
Issue Dt:
|
08/16/2011
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Application #:
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12047257
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Filing Dt:
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03/12/2008
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Publication #:
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Pub Dt:
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09/17/2009
| | | | |
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Title:
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EFFICIENT, SCALABLE AND HIGH PERFORMANCE MECHANISM FOR HANDLING IO REQUESTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
12058117
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Filing Dt:
|
03/28/2008
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Publication #:
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Pub Dt:
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10/01/2009
| | | | |
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Title:
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MECHANISM FOR MAINTAINING CONSISTENCY OF DATA WRITTEN BY IO DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
07/24/2012
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Application #:
|
12060204
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Filing Dt:
|
03/31/2008
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Publication #:
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Pub Dt:
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10/01/2009
| | | | |
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Title:
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APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PROCESSOR SYSTEM
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|
|
|
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
|
12060214
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Filing Dt:
|
03/31/2008
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Publication #:
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Pub Dt:
|
10/01/2009
| | | | |
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Title:
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APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/29/2010
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Application #:
|
12104308
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Filing Dt:
|
04/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
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Title:
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METHOD FOR LATEST PRODUCER TRACKING IN AN OUT-OF-ORDER PROCESSOR, AND APPLICATIONS THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
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Application #:
|
12173560
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Filing Dt:
|
07/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
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Title:
|
FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTISTREAMING PROCESSORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
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Application #:
|
12185587
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Filing Dt:
|
08/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
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Title:
|
MICROPROCESSOR WITH IMPROVED DATA STREAM PREFETCHING USING MULTIPLE TRANSACTION LOOK-ASIDE BUFFERS (TLBs)
|
|
|
|
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Patent #:
|
|
Issue Dt:
|
12/13/2011
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Application #:
|
12185594
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Filing Dt:
|
08/04/2008
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|
Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
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Title:
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METHOD AND APPARATUS FOR PREDICTING CHARACTERISTICS OF INCOMING DATA PACKETS TO ENABLE SPECULATIVE PROCESSING TO REDUCE PROCESSOR LATENCY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/05/2010
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Application #:
|
12187631
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Filing Dt:
|
08/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
|
Title:
|
TRACE CONTROL FROM HARDWARE AND SOFTWARE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12194936
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Filing Dt:
|
08/20/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
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Title:
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DATA CACHE WAY PREDICTION
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|
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Patent #:
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Issue Dt:
|
12/04/2012
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Application #:
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12195053
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Filing Dt:
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08/20/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
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Title:
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DATA CACHE RECEIVE FLOP BYPASS
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
12210150
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Filing Dt:
|
09/12/2008
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Publication #:
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Pub Dt:
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03/18/2010
| | | | |
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Title:
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Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files
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|
|
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Patent #:
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|
Issue Dt:
|
03/01/2011
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Application #:
|
12274104
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Filing Dt:
|
11/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
|
Title:
|
INTERRUPT AND EXCEPTION HANDLING FOR MULTI-STREAMING DIGITAL PROCESSORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
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Application #:
|
12332291
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Filing Dt:
|
12/10/2008
|
|
Publication #:
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Pub Dt:
|
06/18/2009
| | | | |
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Title:
|
COHERENT INSTRUCTION CACHE UTILIZING CACHE-OP EXECUTION RESOURCES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/13/2011
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Application #:
|
12346652
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Filing Dt:
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12/30/2008
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04/30/2009
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Title:
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THREAD INSTRUCTION FETCH BASED ON PRIORITIZED SELECTION FROM PLURAL ROUND-ROBIN OUTPUTS FOR DIFFERENT THREAD STATES
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04/12/2011
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12348181
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01/02/2009
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05/07/2009
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Title:
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METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS
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11/03/2009
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12348847
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01/05/2009
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05/07/2009
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Title:
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HYPERJTAG SYSTEM INCLUDING DEBUG PROBE, ON-CHIP INSTRUMENTATION, AND PROTOCOL
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NONE
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12357929
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01/22/2009
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05/21/2009
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Title:
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Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption
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05/21/2013
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12399330
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03/06/2009
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08/06/2009
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Title:
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SUBSTITUTING PORTION OF TEMPLATE INSTRUCTION PARAMETER WITH SELECTED VIRTUAL INSTRUCTION PARAMETER
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NONE
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12409363
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03/23/2009
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10/01/2009
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Title:
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Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor
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NONE
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12411913
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03/26/2009
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07/23/2009
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Title:
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Method and Apparatus for Improved Computer Load and Store Operations
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03/01/2011
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12421268
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04/09/2009
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08/06/2009
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Title:
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MICROPROCESSOR HAVING A POWER-SAVING INSTRUCTION CACHE WAY PREDICTOR AND INSTRUCTION REPLACEMENT SCHEME
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Patent #:
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NONE
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12429029
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04/23/2009
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Pub Dt:
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10/29/2009
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Title:
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APPARATUS FOR STORING INSTRUCTIONS IN A MULTITHREADING MICROPROCESSOR USING SKID BUFFERS
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06/02/2015
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12429655
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04/24/2009
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08/20/2009
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Title:
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Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities
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04/12/2011
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12432227
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04/29/2009
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09/24/2009
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Title:
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INTERRUPT AND EXCEPTION HANDLING FOR MULTI-STREAMING DIGITAL PROCESSORS
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NONE
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12463330
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05/08/2009
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11/12/2009
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Title:
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Microprocessor with Compact Instruction Set Architecture
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03/01/2016
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12464027
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05/11/2009
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11/11/2010
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Title:
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VARIABLE REGISTER AND IMMEDIATE FIELD ENCODING IN AN INSTRUCTION SET ARCHITECTURE
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06/28/2011
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12477059
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06/02/2009
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12/02/2010
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Title:
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APPARATUS AND METHOD FOR FORMING A MIXED SIGNAL CIRCUIT WITH FULLY CUSTOMIZABLE ANALOG CELLS AND PROGRAMMABLE INTERCONNECT
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12/06/2011
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12480414
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06/08/2009
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10/01/2009
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Title:
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PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
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05/22/2012
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12506153
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07/20/2009
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01/20/2011
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APPARATUS AND METHOD FOR PROFILING SOFTWARE PERFORMANCE ON A PROCESSOR WITH NON-UNIQUE VIRTUAL ADDRESSES
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02/22/2011
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12544167
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08/19/2009
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12/17/2009
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METHOD FOR EXTRACTING FIELDS FROM PACKETS HAVING FIELDS SPREAD OVER MORE THAN ONE REGISTER
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07/28/2015
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12563840
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09/21/2009
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01/14/2010
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Title:
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Data Cache Virtual Hint Way Prediction, and Applications Thereof
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12/20/2011
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12649132
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12/29/2009
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04/29/2010
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Title:
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CONTEXT SHARING BETWEEN A STREAMING PROCESSING UNIT (SPU) AND A PACKET MANAGEMENT UNIT (PMU) IN A PACKET PROCESSING ENVIRONMENT
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12/22/2015
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12652598
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01/05/2010
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08/05/2010
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SYSTEM AND METHOD FOR IMPROVING MEMORY TRANSFER
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NONE
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12748102
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03/26/2010
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12/09/2010
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Microprocessor with Compact Instruction Set Architecture
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NONE
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12794370
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06/04/2010
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12/02/2010
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Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
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03/05/2013
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12847772
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07/30/2010
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02/02/2012
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SYSTEM AND METHOD FOR AUTOMATIC HARDWARE INTERRUPT HANDLING
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NONE
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12875268
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09/03/2010
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03/03/2011
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Title:
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Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
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12/13/2011
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12911392
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10/25/2010
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02/17/2011
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MICROPROCESSOR WITH IMPROVED DATA STREAM PREFETCHING
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06/26/2012
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12985680
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01/06/2011
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04/28/2011
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SYSTEM AND METHOD FOR EXTRACTING FIELDS FROM PACKETS HAVING FIELDS SPREAD OVER MORE THAN ONE REGISTER
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10/16/2012
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13027917
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02/15/2011
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06/09/2011
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AUTOMATED DIGITAL CIRCUIT DESIGN TOOL THAT REDUCES OR ELIMINATES ADVERSE TIMING CONSTRAINTS DUE TO AN INHERENT CLOCK SIGNAL SKEW, AND APPLICATIONS THEREOF
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07/31/2012
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13034567
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02/24/2011
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06/23/2011
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APPARATUS AND METHOD FOR CONTROLLING THE EXCLUSIVITY MODE OF A LEVEL-TWO CACHE
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06/18/2013
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13041948
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03/07/2011
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06/23/2011
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INTERRUPT AND EXCEPTION HANDLING FOR MULTI-STREAMING DIGITAL PROCESSORS
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NONE
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13161332
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06/15/2011
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12/20/2012
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Programmable Memory Address
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12/03/2019
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13161354
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06/15/2011
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12/20/2012
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Apparatus and Method for Hardware Initiation of Emulated Instructions
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NONE
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13168870
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06/24/2011
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12/27/2012
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Apparatus and Method for Accelerated Hardware Page Table Walk
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03/05/2013
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13277856
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10/20/2011
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02/09/2012
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CLOCK RATIO CONTROLLER FOR DYNAMIC VOLTAGE AND FREQUENCY SCALED DIGITAL SYSTEMS, AND APPLICATIONS THEREOF
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NONE
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13323006
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12/12/2011
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04/05/2012
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Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
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NONE
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13328781
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12/16/2011
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06/20/2013
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System For Compression Of Fixed Width Values In A Processor Hardware Trace
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12/30/2014
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13358399
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01/25/2012
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07/25/2013
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MERGED FLOATING POINT OPERATION USING A MODEBIT
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NONE
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13360319
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01/27/2012
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11/15/2012
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MULTITHREADED OPERATION OF A MICROPROCESSOR CACHE
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NONE
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13361441
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01/30/2012
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01/31/2013
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SUPPORT FOR MULTIPLE COHERENCE DOMAINS
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NONE
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13404350
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02/24/2012
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08/30/2012
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SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES
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06/30/2015
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13538984
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06/29/2012
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01/02/2014
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Title:
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Carry Look-Ahead Adder with Generate Bits and Propagate Bits Used for Column Sums
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12/29/2015
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13603280
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09/04/2012
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03/06/2014
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Title:
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Embedded Processor with Virtualized Security Controls Using Guest Identifications, a Common Kernel Address Space and Operational Permissions
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NONE
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13609047
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09/10/2012
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03/14/2013
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Title:
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APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION
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