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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	006861/0068			Pages:	6
		Recorded:	02/07/1994
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 16

Patent #:	4167782	Issue Dt:		Application #:	05863092	Filing Dt:
Title:

Patent #:	4157587	Issue Dt:		Application #:	05863095	Filing Dt:
Title:

Patent #:	4313158	Issue Dt:	01/26/1982	Application #:	05968049	Filing Dt:	12/11/1978
Title:	CACHE APPARATUS FOR ENABLING OVERLAP OF INSTRUCTION FETCH OPERATIONS

Patent #:	4322795	Issue Dt:	03/30/1982	Application #:	06114854	Filing Dt:	01/24/1980
Title:	CACHE MEMORY UTILIZNG SELECTIVE CLEARING AND LEAST RECENTLY USED UPDATING

Patent #:	4371927	Issue Dt:	02/01/1983	Application #:	06131739	Filing Dt:	03/20/1980
Title:	DATA PROCESSING SYSTEM PROGRAMMABLE PRE-READ CAPABILITY

Patent #:	4363095	Issue Dt:	12/07/1982	Application #:	06221851	Filing Dt:	12/31/1980
Title:	HIT/MISS LOGIC FOR A CACHE MEMORY

Patent #:	4521850	Issue Dt:	06/04/1985	Application #:	06433569	Filing Dt:	10/04/1982
Title:	INSTRUCTION BUFFER ASSOCIATED WITH A CACHE MEMORY UNIT

Patent #:	4594659	Issue Dt:	06/10/1986	Application #:	06434197	Filing Dt:	10/13/1982
Title:	METHOD AND APPARATUS FOR PREFETCHING INSTRUCTIONS FOR A CENTRAL EXECUTION PIPELINE UNIT

Patent #:	4695943	Issue Dt:	09/22/1987	Application #:	06655473	Filing Dt:	09/27/1984
Title:	MULTIPROCESSOR SHARED PIPELINE CACHE MEMORY WITH SPLIT CYCLE AND CONCURRENT UTILIZATION

Patent #:	4901222	Issue Dt:	02/13/1990	Application #:	07052108	Filing Dt:	05/19/1987
Title:	A METHOD AND APPARATUS FOR BACKING OUT OF A SOFTWARE INSTRUCTION AFTER EXECUTION HAS BEGUN

Patent #:	4942547	Issue Dt:	07/17/1990	Application #:	07131246	Filing Dt:	12/07/1987
Title:	MULTIPROCESSORS ON A SINGLE SEMICONDUCTOR CHIP

Patent #:	5123097	Issue Dt:	06/16/1992	Application #:	07294529	Filing Dt:	01/05/1989
Title:	APPARATUS AND METHOD FOR SIMULTANEOUS EXECUTION OF A WRITE INSTRUCTION AND A SUCCEEDING READ INSTRUCTION IN A DATA PROCESSING SYSTEM WITH A STORE THROUGH CACHE STRATEGY

Patent #:	5148533	Issue Dt:	09/15/1992	Application #:	07294534	Filing Dt:	01/05/1989
Title:	APPARATUS AND METHOD FOR DATA GROUP COHERENCY IN A TIGHTLY COUPLED DATA PROCESSING SYSTEM WITH PLURAL EXECUTION AND DATA CACHE UNITS

Patent #:	5093777	Issue Dt:	03/03/1992	Application #:	07364943	Filing Dt:	06/12/1989
Title:	METHOD AND APPARATUS FOR PREDICTING ADDRESS OF A SUBSEQUENT CACHE REQUEST UPON ANALTZING ADDRESS PATTERNS STORED IN SEPARATE MISS STACK

Patent #:	5073855	Issue Dt:	12/17/1991	Application #:	07374882	Filing Dt:	06/30/1989
Title:	RESOURCE CONFLICT DETECTION METHOD AND APPARATUS INCLUDED IN A PIPE- LINED PROCESSING UNIT

Patent #:	5119495	Issue Dt:	06/02/1992	Application #:	07454222	Filing Dt:	12/21/1989
Title:	MINIMIZING HARDWARE PIPELINE BREAKS USING SOFTWARE SCHEDULING TECHNIQUES DURING COMPILATION

Assignor

Exec Dt:

01/26/1994

Assignee

2200 MISSION COLLEGE BLVD.

SANTA CLARA, CALIFORNIA 95052

Correspondence name and address
	JAMES H. SALTER
	12400 WILSHIRE BLVD.
	SEVENTH FLOOR
	LOS ANGELES, CA 90025

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