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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	023282/0070			Pages:	12
		Recorded:	09/21/2009
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 27

1

Patent #:	6737879	Issue Dt:	05/18/2004	Application #:	10176571	Filing Dt:	06/21/2002
Publication #:	US20020196046	Pub Dt:	12/26/2002
Title:	METHOD AND APPARATUS FOR WAFER SCALE TESTING

2

Patent #:	6991969	Issue Dt:	01/31/2006	Application #:	10370393	Filing Dt:	02/19/2003
Publication #:	US20040161880	Pub Dt:	08/19/2004
Title:	METHODS AND APPARATUS FOR ADDITION OF ELECTRICAL CONDUCTORS TO PREVIOUSLY FABRICATED DEVICE

3

Patent #:	6836130	Issue Dt:	12/28/2004	Application #:	10633011	Filing Dt:	08/01/2003
Publication #:	US20040027151	Pub Dt:	02/12/2004
Title:	METHOD AND APPARATUS FOR WAFER SCALE TESTING

4

Patent #:	7282931	Issue Dt:	10/16/2007	Application #:	10789305	Filing Dt:	02/27/2004
Publication #:	US20040164295	Pub Dt:	08/26/2004
Title:	FULL WAFER CONTACTER AND APPLICATIONS THEREOF

5

Patent #:	7638366	Issue Dt:	12/29/2009	Application #:	11339102	Filing Dt:	01/23/2006
Publication #:	US20060121648	Pub Dt:	06/08/2006
Title:	METHODS AND APPARATUS FOR ADDITION OF ELECTRICAL CONDUCTORS TO PREVIOUSLY FABRICATED DEVICE

6

Patent #:	NONE	Issue Dt:		Application #:	11729039	Filing Dt:	03/27/2007
Publication #:	US20070229105	Pub Dt:	10/04/2007
Title:	Desktop wafer analysis station

7

Patent #:	7379641	Issue Dt:	05/27/2008	Application #:	11799550	Filing Dt:	05/01/2007
Title:	FIBER-BASED OPTICAL ALIGNMENT SYSTEM

8

Patent #:	7456643	Issue Dt:	11/25/2008	Application #:	11810237	Filing Dt:	06/05/2007
Publication #:	US20070296449	Pub Dt:	12/27/2007
Title:	METHODS FOR MULTI-MODAL WAFER TESTING USING EDGE-EXTENDED WAFER TRANSLATOR

9

Patent #:	7453277	Issue Dt:	11/18/2008	Application #:	11810950	Filing Dt:	06/06/2007
Publication #:	US20080074135	Pub Dt:	03/27/2008
Title:	APPARATUS FOR FULL-WAFER TEST AND BURN-IN MECHANISM

10

Patent #:	7532021	Issue Dt:	05/12/2009	Application #:	11810951	Filing Dt:	06/06/2007
Publication #:	US20080218192	Pub Dt:	09/11/2008
Title:	APPARATUS FOR TRANSLATED WAFER STAND-IN TESTER

11

Patent #:	7532022	Issue Dt:	05/12/2009	Application #:	11811874	Filing Dt:	06/11/2007
Publication #:	US20080001617	Pub Dt:	01/03/2008
Title:	APPARATUS FOR FIXED-FORM MULTI-PLANAR EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE MARGINS OF A SUBSTRATE

12

Patent #:	NONE	Issue Dt:		Application #:	11811880	Filing Dt:	06/11/2007
Publication #:	US20080003819	Pub Dt:	01/03/2008
Title:	Laser isolation of metal over alumina underlayer and structures formed thereby

13

Patent #:	7459924	Issue Dt:	12/02/2008	Application #:	11825567	Filing Dt:	07/06/2007
Publication #:	US20080018341	Pub Dt:	01/24/2008
Title:	APPARATUS FOR PROVIDING ELECTRICAL ACCESS TO ONE OR MORE PADS OF THE WAFER USING A WAFER TRANSLATOR AND A GASKET.

14

Patent #:	7572132	Issue Dt:	08/11/2009	Application #:	11879736	Filing Dt:	07/17/2007
Publication #:	US20080248663	Pub Dt:	10/09/2008
Title:	METHODS AND APPARATUS FOR FLEXIBLE EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE EDGES OF A SUBSTRATE

15

Patent #:	7498800	Issue Dt:	03/03/2009	Application #:	11880093	Filing Dt:	07/18/2007
Title:	METHODS AND APPARATUS FOR ROTATIONALLY ACCESSED TESTER INTERFACE

16

Patent #:	7489148	Issue Dt:	02/10/2009	Application #:	11881574	Filing Dt:	07/27/2007
Publication #:	US20080048696	Pub Dt:	02/28/2008
Title:	METHODS FOR ACCESS TO A PLURALITY OF UNSINGULATED INTEGRATED CIRCUITS OF A WAFER USING SINGLE-SIDED EDGE-EXTENDED WAFER TRANSLATOR

17

Patent #:	NONE	Issue Dt:		Application #:	12074904	Filing Dt:	03/07/2008
Publication #:	US20090224410	Pub Dt:	09/10/2009
Title:	Wafer translator having a silicon core fabricated with printed circuit board manufacturing techniques

18

Patent #:	7791174	Issue Dt:	09/07/2010	Application #:	12077670	Filing Dt:	03/20/2008
Publication #:	US20090224372	Pub Dt:	09/10/2009
Title:	WAFER TRANSLATOR HAVING A SILICON CORE ISOLATED FROM SIGNAL PATHS BY A GROUND PLANE

19

Patent #:	7723980	Issue Dt:	05/25/2010	Application #:	12079159	Filing Dt:	03/24/2008
Publication #:	US20080230927	Pub Dt:	09/25/2008
Title:	FULLY TESTED WAFERS HAVING BOND PADS UNDAMAGED BY PROBING AND APPLICATIONS THEREOF

20

Patent #:	7579852	Issue Dt:	08/25/2009	Application #:	12079202	Filing Dt:	03/24/2008
Publication #:	US20080231302	Pub Dt:	09/25/2008
Title:	WAFER TRANSLATOR HAVING METALLIZATION PATTERN PROVIDING HIGH DENSITY INTERDIGITATED CONTACT PADS FOR COMPONENT

21

Patent #:	7460752	Issue Dt:	12/02/2008	Application #:	12154684	Filing Dt:	05/24/2008
Publication #:	US20080273847	Pub Dt:	11/06/2008
Title:	FIBER-BASED OPTICAL ALIGNMENT SYSTEM

22

Patent #:	8536062	Issue Dt:	09/17/2013	Application #:	12284618	Filing Dt:	09/22/2008
Publication #:	US20090081875	Pub Dt:	03/26/2009
Title:	CHEMICAL REMOVAL OF OXIDE LAYER FROM CHIP PADS

23

Patent #:	7724008	Issue Dt:	05/25/2010	Application #:	12325269	Filing Dt:	12/01/2008
Publication #:	US20090189627	Pub Dt:	07/30/2009
Title:	METHODS AND APPARATUS FOR PLANAR EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE EDGES OF A SUBSTRATE

24

Patent #:	7786745	Issue Dt:	08/31/2010	Application #:	12347995	Filing Dt:	12/31/2008
Publication #:	US20100001750	Pub Dt:	01/07/2010
Title:	METHOD AND APPARATUS FOR SINGLE-SIDED EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE EDGES OF A SUBSTRATE

25

Patent #:	NONE	Issue Dt:		Application #:	12404277	Filing Dt:	03/13/2009
Publication #:	US20100066395	Pub Dt:	03/18/2010
Title:	Wafer Prober Integrated With Full-Wafer Contacter

26

Patent #:	7786724	Issue Dt:	08/31/2010	Application #:	12427748	Filing Dt:	04/22/2009
Title:	METHODS AND APPARATUS FOR COLLECTING PROCESS CHARACTERIZATION DATA AFTER FIRST FAILURE IN A GROUP OF TESTED DEVICES

27

Patent #:	8362797	Issue Dt:	01/29/2013	Application #:	12547418	Filing Dt:	08/25/2009
Publication #:	US20110050274	Pub Dt:	03/03/2011
Title:	MAINTAINING A WAFER/WAFER TRANSLATOR PAIR IN AN ATTACHED STATE FREE OF A GASKET DISPOSED THEREBETWEEN

Assignor

1

ADVANCED INQUIRY SYSTEMS, INC.

Exec Dt:

09/11/2009

Assignees

1

PENINSULA MASTER FUND, LTD.

235 PINE STREET, SUITE 1600

235 PINE STREET, SUITE 1600

SAN FRANCISCO, CALIFORNIA 94104

2

PENINSULA TECHNOLOGY FUND, LP

235 PINE STREET, SUITE 1600

SAN FRANCISCO, CALIFORNIA 94104

3

1177 AVENUE OF THE AMERICAS, 9TH FLOOR

NEW YORK, NEW YORK 10036

4

QUINTESSENCE FUND LP

1177 AVENUE OF THE AMERICAS, 9TH FLOOR

NEW YORK, NEW YORK 10036

Correspondence name and address
	GARY SERBIN, ESQ.
	590 MADISON AVENUE, 6TH FLOOR
	LOVELLS LLP
	NEW YORK, NEW YORK 10022

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