Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 049768/0076 | |
| Pages: | 5 |
| | Recorded: | 07/16/2019 | | |
Attorney Dkt #: | 1016.IVY |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13749682
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Filing Dt:
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01/25/2013
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Publication #:
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Pub Dt:
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07/31/2014
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Title:
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Apparatus For Design-Based Manufacturing Optimization In Semiconductor Fab
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Patent #:
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Issue Dt:
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09/22/2015
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Application #:
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13906303
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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SYSTEM AND METHOD FOR IDENTIFYING SYSTEMATIC DEFECTS IN WAFER INSPECTION USING HIERARCHICAL GROUPING AND FILTERING
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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14150772
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Filing Dt:
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01/09/2014
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Title:
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DESIGN SIGNATURE ANALYTICS FOR IMPROVING LITHOGRAPHIC PROCESS OF MANUFACTURING SEMICONDUCTOR DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14607352
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Filing Dt:
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01/28/2015
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Publication #:
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Pub Dt:
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07/28/2016
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Title:
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Methodology Of Incorporating Wafer Physical Measurement With Digital Simulation For Improving Semiconductor Device Fabrication
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Patent #:
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Issue Dt:
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01/17/2017
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Application #:
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14810428
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Filing Dt:
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07/27/2015
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Publication #:
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Pub Dt:
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02/02/2017
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Title:
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System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing
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Patent #:
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Issue Dt:
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07/30/2019
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Application #:
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15375186
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Filing Dt:
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12/12/2016
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Publication #:
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Pub Dt:
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06/14/2018
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Title:
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AUTO DEFECT SCREENING USING ADAPTIVE MACHINE LEARNING IN SEMICONDUCTOR DEVICE MANUFACTURING FLOW
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Assignee
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3050 BOWERS AVENUE |
SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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PATTERSON + SHERIDAN LLP
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24 GREENWAY PLAZA
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SUITE 1600
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HOUSTON, TX 77046
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