skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:035782/0078   Pages: 3
Recorded: 05/26/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
01/19/2016
Application #:
14712864
Filing Dt:
05/14/2015
Publication #:
Pub Dt:
11/19/2015
Title:
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
Assignor
1
Exec Dt:
05/22/2015
Assignee
1
2570 W. EL CAMINO REAL, SUITE 210
MOUNTAIN VIEW, CALIFORNIA 94040
Correspondence name and address
NEIL A. STEINBERG
5335 WISCONSIN AVE, NW SUITE 440
WASHINGTON, D.C. 20015

Search Results as of: 06/16/2024 09:54 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT