USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	056696/0081			Pages:	7
		Recorded:	06/28/2021
Attorney Dkt #:	VARIOUS
Conveyance:	MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 93

Patent #:	8161422	Issue Dt:	04/17/2012	Application #:	12349108	Filing Dt:	01/06/2009
Publication #:	US20100175043	Pub Dt:	07/08/2010
Title:	FAST AND ACCURATE METHOD TO SIMULATE INTERMEDIATE RANGE FLARE EFFECTS

Patent #:	8141025	Issue Dt:	03/20/2012	Application #:	12354306	Filing Dt:	01/15/2009
Publication #:	US20100180243	Pub Dt:	07/15/2010
Title:	METHOD OF PERFORMING TIMING ANALYSIS ON INTEGRATED CIRCUIT CHIPS WITH CONSIDERATION OF PROCESS VARIATIONS

Patent #:	8127261	Issue Dt:	02/28/2012	Application #:	12356116	Filing Dt:	01/20/2009
Publication #:	US20100185992	Pub Dt:	07/22/2010
Title:	SYSTEM FOR QUICKLY SPECIFYING FORMAL VERIFICATION ENVIRONMENTS

Patent #:	8151240	Issue Dt:	04/03/2012	Application #:	12416222	Filing Dt:	04/01/2009
Publication #:	US20100257493	Pub Dt:	10/07/2010
Title:	EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS

Patent #:	8136069	Issue Dt:	03/13/2012	Application #:	12423387	Filing Dt:	04/14/2009
Publication #:	US20100262940	Pub Dt:	10/14/2010
Title:	ACCURATE APPROXIMATION OF RESISTANCE IN A WIRE WITH IRREGULAR BIASING AND DETERMINATION OF INTERCONNECT CAPACITANCES IN VLSI LAYOUTS IN THE PRESENCE OF CATASTROPHIC OPTICAL PROXIMITY CORRECTION

Patent #:	8667434	Issue Dt:	03/04/2014	Application #:	12478658	Filing Dt:	06/04/2009
Title:	SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ALTERING A HARDWARE DESCRIPTION BASED ON AN INSTRUCTION FILE

Patent #:	8166444	Issue Dt:	04/24/2012	Application #:	12489441	Filing Dt:	06/23/2009
Publication #:	US20100325596	Pub Dt:	12/23/2010
Title:	CLOCK GATING USING ABSTRACTION REFINEMENT

Patent #:	8141014	Issue Dt:	03/20/2012	Application #:	12538229	Filing Dt:	08/10/2009
Publication #:	US20110035714	Pub Dt:	02/10/2011
Title:	SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS

Patent #:	8141012	Issue Dt:	03/20/2012	Application #:	12549061	Filing Dt:	08/27/2009
Publication #:	US20110055793	Pub Dt:	03/03/2011
Title:	TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN

Patent #:	8171442	Issue Dt:	05/01/2012	Application #:	12557872	Filing Dt:	09/11/2009
Publication #:	US20110066989	Pub Dt:	03/17/2011
Title:	METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS

Patent #:	8181134	Issue Dt:	05/15/2012	Application #:	12580373	Filing Dt:	10/16/2009
Publication #:	US20110093824	Pub Dt:	04/21/2011
Title:	TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN

Patent #:	8146026	Issue Dt:	03/27/2012	Application #:	12619742	Filing Dt:	11/17/2009
Publication #:	US20110119642	Pub Dt:	05/19/2011
Title:	SIMULTANEOUS PHOTOLITHOGRAPHIC MASK AND TARGET OPTIMIZATION

Patent #:	8141027	Issue Dt:	03/20/2012	Application #:	12652409	Filing Dt:	01/05/2010
Publication #:	US20110166686	Pub Dt:	07/07/2011
Title:	AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS

Patent #:	8108821	Issue Dt:	01/31/2012	Application #:	12685803	Filing Dt:	01/12/2010
Publication #:	US20110173584	Pub Dt:	07/14/2011
Title:	REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION

Patent #:	8621413	Issue Dt:	12/31/2013	Application #:	12723539	Filing Dt:	03/12/2010
Title:	SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR REDUCING A DEACTIVATION FUNCTION UTILIZING AN OPTIMAL REDUCTION

Patent #:	8181131	Issue Dt:	05/15/2012	Application #:	12771613	Filing Dt:	04/30/2010
Publication #:	US20110271244	Pub Dt:	11/03/2011
Title:	ENHANCED ANALYSIS OF ARRAY-BASED NETLISTS VIA REPARAMETERIZATION

Patent #:	8146034	Issue Dt:	03/27/2012	Application #:	12771677	Filing Dt:	04/30/2010
Publication #:	US20110271242	Pub Dt:	11/03/2011
Title:	EFFICIENT REDUNDANCY IDENTIFICATION, REDUNDANCY REMOVAL, AND SEQUENTIAL EQUIVALENCE CHECKING WITHIN DESIGNS INCLUDING MEMORY ARRAYS

Patent #:	9720859	Issue Dt:	08/01/2017	Application #:	12772051	Filing Dt:	04/30/2010
Title:	SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONDITIONALLY ELIMINATING A MEMORY READ REQUEST

Patent #:	8291359	Issue Dt:	10/16/2012	Application #:	12775633	Filing Dt:	05/07/2010
Publication #:	US20110276932	Pub Dt:	11/10/2011
Title:	ARRAY CONCATENATION IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	8473533	Issue Dt:	06/25/2013	Application #:	12818032	Filing Dt:	06/17/2010
Title:	METHOD AND APPARATUS FOR HARMONIC BALANCE USING DIRECT SOLUTION OF HB JACOBIAN

Patent #:	8271240	Issue Dt:	09/18/2012	Application #:	12859531	Filing Dt:	08/19/2010
Publication #:	US20120046922	Pub Dt:	02/23/2012
Title:	SECURE CLOUD-BASED ELECTRONIC DESIGN AUTOMATION

Patent #:	8352891	Issue Dt:	01/08/2013	Application #:	12859743	Filing Dt:	08/19/2010
Publication #:	US20120047473	Pub Dt:	02/23/2012
Title:	LAYOUT DECOMPOSITION BASED ON PARTIAL INTENSITY DISTRIBUTION

Patent #:	8688414	Issue Dt:	04/01/2014	Application #:	13018103	Filing Dt:	01/31/2011
Publication #:	US20120192641	Pub Dt:	08/02/2012
Title:	IDENTIFICATION OF FLUID FLOW BOTTLENECKS

Patent #:	8539406	Issue Dt:	09/17/2013	Application #:	13018229	Filing Dt:	01/31/2011
Publication #:	US20120198398	Pub Dt:	08/02/2012
Title:	EQUIVALENCE CHECKING FOR RETIMED ELECTRONIC CIRCUIT DESIGNS

Patent #:	8239789	Issue Dt:	08/07/2012	Application #:	13080148	Filing Dt:	04/05/2011
Publication #:	US20110184715	Pub Dt:	07/28/2011
Title:	SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN

Patent #:	8494670	Issue Dt:	07/23/2013	Application #:	13081030	Filing Dt:	04/06/2011
Publication #:	US20120259446	Pub Dt:	10/11/2012
Title:	MONTE-CARLO BASED ACCURATE CORNER EXTRACTION

Patent #:	8302040	Issue Dt:	10/30/2012	Application #:	13100584	Filing Dt:	05/04/2011
Publication #:	US20110225562	Pub Dt:	09/15/2011
Title:	COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE

Patent #:	8136082	Issue Dt:	03/13/2012	Application #:	13102249	Filing Dt:	05/06/2011
Publication #:	US20110214102	Pub Dt:	09/01/2011
Title:	METHOD FOR TESTING INTEGRATED CIRCUITS

Patent #:	8689069	Issue Dt:	04/01/2014	Application #:	13157237	Filing Dt:	06/09/2011
Publication #:	US20120317454	Pub Dt:	12/13/2012
Title:	MULTI-TARGETING BOOLEAN SATISFIABILITY-BASED TEST PATTERN GENERATION

Patent #:	8136079	Issue Dt:	03/13/2012	Application #:	13187201	Filing Dt:	07/20/2011
Publication #:	US20110283251	Pub Dt:	11/17/2011
Title:	EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS

Patent #:	8402397	Issue Dt:	03/19/2013	Application #:	13191433	Filing Dt:	07/26/2011
Publication #:	US20130031522	Pub Dt:	01/31/2013
Title:	HOTSPOT DETECTION BASED ON MACHINE LEARNING

Patent #:	8504949	Issue Dt:	08/06/2013	Application #:	13191436	Filing Dt:	07/26/2011
Publication #:	US20130031518	Pub Dt:	01/31/2013
Title:	HYBRID HOTSPOT DETECTION

Patent #:	8239790	Issue Dt:	08/07/2012	Application #:	13216362	Filing Dt:	08/24/2011
Publication #:	US20110307846	Pub Dt:	12/15/2011
Title:	METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD

Patent #:	8990760	Issue Dt:	03/24/2015	Application #:	13219564	Filing Dt:	08/26/2011
Publication #:	US20130054161	Pub Dt:	02/28/2013
Title:	Cell-Aware Fault Model Generation For Delay Faults

Patent #:	8352893	Issue Dt:	01/08/2013	Application #:	13235153	Filing Dt:	09/16/2011
Title:	CIRCUIT TOPOLOGY RECOGNITION AND CIRCUIT PARTITIONING

Patent #:	8539393	Issue Dt:	09/17/2013	Application #:	13244070	Filing Dt:	09/23/2011
Publication #:	US20130080982	Pub Dt:	03/28/2013
Title:	SIMULATION AND CORRECTION OF MASK SHADOWING EFFECT

Patent #:	8935643	Issue Dt:	01/13/2015	Application #:	13267874	Filing Dt:	10/06/2011
Publication #:	US20130091479	Pub Dt:	04/11/2013
Title:	PARAMETER MATCHING HOTSPOT DETECTION

Patent #:	8533636	Issue Dt:	09/10/2013	Application #:	13279176	Filing Dt:	10/21/2011
Publication #:	US20130104091	Pub Dt:	04/25/2013
Title:	TOLERABLE FLARE DIFFERENCE DETERMINATION

Patent #:	8572533	Issue Dt:	10/29/2013	Application #:	13304099	Filing Dt:	11/23/2011
Publication #:	US20130132918	Pub Dt:	05/23/2013
Title:	WAIVING DENSITY VIOLATIONS

Patent #:	8504975	Issue Dt:	08/06/2013	Application #:	13344178	Filing Dt:	01/05/2012
Publication #:	US20120105240	Pub Dt:	05/03/2012
Title:	RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS

Patent #:	8719747	Issue Dt:	05/06/2014	Application #:	13362605	Filing Dt:	01/31/2012
Publication #:	US20130198701	Pub Dt:	08/01/2013
Title:	SINGLE EVENT UPSET MITIGATION FOR ELECTRONIC DESIGN SYNTHESIS

Patent #:	8539391	Issue Dt:	09/17/2013	Application #:	13363343	Filing Dt:	01/31/2012
Publication #:	US20130198698	Pub Dt:	08/01/2013
Title:	EDGE FRAGMENT CORRELATION DETERMINATION FOR OPTICAL PROXIMITY CORRECTION

Patent #:	9183330	Issue Dt:	11/10/2015	Application #:	13363345	Filing Dt:	01/31/2012
Publication #:	US20130198704	Pub Dt:	08/01/2013
Title:	ESTIMATION OF POWER AND THERMAL PROFILES

Patent #:	8683394	Issue Dt:	03/25/2014	Application #:	13363348	Filing Dt:	01/31/2012
Publication #:	US20130198699	Pub Dt:	08/01/2013
Title:	PATTERN MATCHING OPTICAL PROXIMITY CORRECTION

Patent #:	8887113	Issue Dt:	11/11/2014	Application #:	13364249	Filing Dt:	02/01/2012
Publication #:	US20120192128	Pub Dt:	07/26/2012
Title:	COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN

Patent #:	8739086	Issue Dt:	05/27/2014	Application #:	13364256	Filing Dt:	02/01/2012
Publication #:	US20120192129	Pub Dt:	07/26/2012
Title:	COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN

Patent #:	8499263	Issue Dt:	07/30/2013	Application #:	13434788	Filing Dt:	03/29/2012
Title:	ENCRYPTED PROFILES FOR PARASITIC EXTRACTION

Patent #:	8429576	Issue Dt:	04/23/2013	Application #:	13471789	Filing Dt:	05/15/2012
Publication #:	US20120227019	Pub Dt:	09/06/2012
Title:	METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD

Patent #:	8504962	Issue Dt:	08/06/2013	Application #:	13526442	Filing Dt:	06/18/2012
Title:	Through-Silicon Via Admittance Extraction

Patent #:	8539401	Issue Dt:	09/17/2013	Application #:	13609121	Filing Dt:	09/10/2012
Publication #:	US20130007688	Pub Dt:	01/03/2013
Title:	GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION

Patent #:	8826196	Issue Dt:	09/02/2014	Application #:	13754378	Filing Dt:	01/30/2013
Publication #:	US20140215416	Pub Dt:	07/31/2014
Title:	Integration of Optical Proximity Correction and Mask Data Preparation

Patent #:	8930856	Issue Dt:	01/06/2015	Application #:	13754421	Filing Dt:	01/30/2013
Publication #:	US20140215414	Pub Dt:	07/31/2014
Title:	Mask Rule Checking Based on Curvature

Patent #:	9201994	Issue Dt:	12/01/2015	Application #:	13802083	Filing Dt:	03/13/2013
Title:	FLEXIBLE POWER QUERY INTERFACES AND INFRASTRUCTURES

Patent #:	8977997	Issue Dt:	03/10/2015	Application #:	13842174	Filing Dt:	03/15/2013
Publication #:	US20140282312	Pub Dt:	09/18/2014
Title:	HARDWARE SIMULATION CONTROLLER, SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION

Patent #:	9335377	Issue Dt:	05/10/2016	Application #:	13919974	Filing Dt:	06/17/2013
Publication #:	US20140372818	Pub Dt:	12/18/2014
Title:	TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS

Patent #:	8978002	Issue Dt:	03/10/2015	Application #:	14013925	Filing Dt:	08/29/2013
Publication #:	US20150067627	Pub Dt:	03/05/2015
Title:	RAPID EXPRESSION COVERAGE

Patent #:	9294412	Issue Dt:	03/22/2016	Application #:	14013941	Filing Dt:	08/29/2013
Publication #:	US20150063120	Pub Dt:	03/05/2015
Title:	CONTROLLER AREA NETWORK (CAN) WORST-CASE MESSAGE LATENCY WITH PRIORITY INVERSION

Patent #:	9407573	Issue Dt:	08/02/2016	Application #:	14013959	Filing Dt:	08/29/2013
Publication #:	US20150063371	Pub Dt:	03/05/2015
Title:	BANDWIDTH CONTROL IN A CONTROLLER AREA NETWORK (CAN)

Patent #:	8832633	Issue Dt:	09/09/2014	Application #:	14028336	Filing Dt:	09/16/2013
Publication #:	US20140013289	Pub Dt:	01/09/2014
Title:	GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION

Patent #:	9946823	Issue Dt:	04/17/2018	Application #:	14041211	Filing Dt:	09/30/2013
Publication #:	US20150046144	Pub Dt:	02/12/2015
Title:	Dynamic Control Of Design Clock Generation In Emulation

Patent #:	9032357	Issue Dt:	05/12/2015	Application #:	14083050	Filing Dt:	11/18/2013
Publication #:	US20150143323	Pub Dt:	05/21/2015
Title:	Generating Guiding Patterns For Directed Self-Assembly

Patent #:	9165099	Issue Dt:	10/20/2015	Application #:	14087531	Filing Dt:	11/22/2013
Publication #:	US20150100931	Pub Dt:	04/09/2015
Title:	Adaptive Clock Management In Emulation

Patent #:	9135391	Issue Dt:	09/15/2015	Application #:	14090294	Filing Dt:	11/26/2013
Publication #:	US20150143318	Pub Dt:	05/21/2015
Title:	DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS

Patent #:	9805156	Issue Dt:	10/31/2017	Application #:	14142201	Filing Dt:	12/27/2013
Publication #:	US20150186591	Pub Dt:	07/02/2015
Title:	SELECTIVE PARASITIC EXTRACTION

Patent #:	9607122	Issue Dt:	03/28/2017	Application #:	14168363	Filing Dt:	01/30/2014
Publication #:	US20150213186	Pub Dt:	07/30/2015
Title:	TIMING DRIVEN CLOCK TREE SYNTHESIS

Patent #:	9811617	Issue Dt:	11/07/2017	Application #:	14168817	Filing Dt:	01/30/2014
Publication #:	US20150213169	Pub Dt:	07/30/2015
Title:	REGRESSION NEAREST NEIGHBOR ANALYSIS FOR STATISTICAL FUNCTIONAL COVERAGE

Patent #:	10445699	Issue Dt:	10/15/2019	Application #:	14168834	Filing Dt:	01/30/2014
Publication #:	US20150213407	Pub Dt:	07/30/2015
Title:	SOCIAL ELECTRONIC DESIGN AUTOMATION

Patent #:	9824169	Issue Dt:	11/21/2017	Application #:	14168884	Filing Dt:	01/30/2014
Publication #:	US20150213174	Pub Dt:	07/30/2015
Title:	REGRESSION SIGNATURE FOR STATISTICAL FUNCTIONAL COVERAGE

Patent #:	8930878	Issue Dt:	01/06/2015	Application #:	14168912	Filing Dt:	01/30/2014
Title:	SYSTEM TO COMBAT DESIGN-TIME VULNERABILITY

Patent #:	8910098	Issue Dt:	12/09/2014	Application #:	14183209	Filing Dt:	02/18/2014
Title:	NEIGHBOR-AWARE EDGE FRAGMENT ADJUSTMENT FOR OPTICAL PROXIMITY CORRECTION

Patent #:	8881070	Issue Dt:	11/04/2014	Application #:	14183228	Filing Dt:	02/18/2014
Title:	OPTICAL PROXIMITY CORRECTION BASED ON EDGE FRAGMENT CORRELATION

Patent #:	9305126	Issue Dt:	04/05/2016	Application #:	14222404	Filing Dt:	03/21/2014
Publication #:	US20150269295	Pub Dt:	09/24/2015
Title:	Switching Activity Reduction Through Retiming

Patent #:	10599881	Issue Dt:	03/24/2020	Application #:	14225274	Filing Dt:	03/25/2014
Title:	Circuit Simulation Waveform Generation and Display

Patent #:	9459523	Issue Dt:	10/04/2016	Application #:	14253171	Filing Dt:	04/15/2014
Publication #:	US20150294053	Pub Dt:	10/15/2015
Title:	Pattern Optical Similarity Determination

Patent #:	9703916	Issue Dt:	07/11/2017	Application #:	14473914	Filing Dt:	08/29/2014
Publication #:	US20150220677	Pub Dt:	08/06/2015
Title:	STREAMING, AT-SPEED DEBUG AND VALIDATION ARCHITECTURE

Patent #:	9673819	Issue Dt:	06/06/2017	Application #:	14473922	Filing Dt:	08/29/2014
Publication #:	US20170141764	Pub Dt:	05/18/2017
Title:	METASTABILITY GLITCH DETECTION

Patent #:	9483594	Issue Dt:	11/01/2016	Application #:	14476384	Filing Dt:	09/03/2014
Publication #:	US20160063161	Pub Dt:	03/03/2016
Title:	RESET VERIFICATION

Patent #:	9678435	Issue Dt:	06/13/2017	Application #:	14493073	Filing Dt:	09/22/2014
Title:	Horizontal Development Bias In Negative Tone Development Of Photoresist

Patent #:	9940428	Issue Dt:	04/10/2018	Application #:	14508825	Filing Dt:	10/07/2014
Publication #:	US20160098512	Pub Dt:	04/07/2016
Title:	HIERARCHICAL FILL IN A DESIGN LAYOUT

Patent #:	10360332	Issue Dt:	07/23/2019	Application #:	14549242	Filing Dt:	11/20/2014
Publication #:	US20160147924	Pub Dt:	05/26/2016
Title:	Handling Blind Statements In Mixed Language Environments

Patent #:	10127343	Issue Dt:	11/13/2018	Application #:	14567488	Filing Dt:	12/11/2014
Publication #:	US20160171143	Pub Dt:	06/16/2016
Title:	CIRCUIT DESIGN LAYOUT IN MULTIPLE SYNCHRONOUS REPRESENTATIONS

Patent #:	10438151	Issue Dt:	10/08/2019	Application #:	14580663	Filing Dt:	12/23/2014
Publication #:	US20160180273	Pub Dt:	06/23/2016
Title:	TAKE RATE DETERMINATION

Patent #:	9703917	Issue Dt:	07/11/2017	Application #:	14600430	Filing Dt:	01/20/2015
Publication #:	US20160210394	Pub Dt:	07/21/2016
Title:	Identification Of High Impedance Nodes In A Circuit Design

Patent #:	9679097	Issue Dt:	06/13/2017	Application #:	14608567	Filing Dt:	01/29/2015
Publication #:	US20150220678	Pub Dt:	08/06/2015
Title:	SELECTIVE POWER STATE TABLE COMPOSITION

Patent #:	9836043	Issue Dt:	12/05/2017	Application #:	14608611	Filing Dt:	01/29/2015
Publication #:	US20160224022	Pub Dt:	08/04/2016
Title:	HARNESS SUB-ASSEMBLY RATIONALIZATION

Patent #:	10296693	Issue Dt:	05/21/2019	Application #:	14608626	Filing Dt:	01/29/2015
Publication #:	US20160171144	Pub Dt:	06/16/2016
Title:	THREE-DIMENSIONAL COMPOSITE SOLID COMPONENT MODELING

Patent #:	9477805	Issue Dt:	10/25/2016	Application #:	14609871	Filing Dt:	01/30/2015
Publication #:	US20160224714	Pub Dt:	08/04/2016
Title:	LOGICAL EQUIVALENCY CHECK WITH DYNAMIC MODE CHANGE

Patent #:	10984150	Issue Dt:	04/20/2021	Application #:	14609880	Filing Dt:	01/30/2015
Publication #:	US20160224691	Pub Dt:	08/04/2016
Title:	HARNESS DESIGN CHANGE RECORD AND REPLAY

Patent #:	10747911	Issue Dt:	08/18/2020	Application #:	14615644	Filing Dt:	02/06/2015
Publication #:	US20160171125	Pub Dt:	06/16/2016
Title:	CONSTRAINED FLATTENING OF DESIGN DATA

Patent #:	10387593	Issue Dt:	08/20/2019	Application #:	14630345	Filing Dt:	02/24/2015
Publication #:	US20160246913	Pub Dt:	08/25/2016
Title:	Code Coverage Reconstruction

Patent #:	10325055	Issue Dt:	06/18/2019	Application #:	14678788	Filing Dt:	04/03/2015
Publication #:	US20160292344	Pub Dt:	10/06/2016
Title:	SIGNAL INTEGRITY DELAY UTILIZING A WINDOW BUMP-BASED AGGRESSOR ALIGNMENT SCHEME

Patent #:	9983914	Issue Dt:	05/29/2018	Application #:	14708490	Filing Dt:	05/11/2015
Publication #:	US20160335021	Pub Dt:	11/17/2016
Title:	MEMORY CORRUPTION PROTECTION BY TRACING MEMORY

Patent #:	9817934	Issue Dt:	11/14/2017	Application #:	15220368	Filing Dt:	07/26/2016
Publication #:	US20170053052	Pub Dt:	02/23/2017
Title:	MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

Assignor

MENTOR GRAPHICS CORPORATION

Exec Dt:

12/30/2020

Newly Merged Entity Data

SIEMENS INDUSTRY SOFTWARE INC.

Exec Dt:

12/30/2020

Newly Merged Entity's New Name

SIEMENS INDUSTRY SOFTWARE INC.

5800 GRANITE PARKWAY, SUITE 600

PLANO, TEXAS 75024

Correspondence name and address
	SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
	3850 QUADRANGLE BOULEVARD
	ORLANDO, FL 32817

Search Results as of: 05/27/2024 03:43 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6