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Patent #:
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Issue Dt:
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10/25/2016
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Application #:
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14732680
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Filing Dt:
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06/06/2015
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Publication #:
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Pub Dt:
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09/24/2015
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Title:
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BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME
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Patent #:
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Issue Dt:
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06/14/2016
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Application #:
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14732689
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Filing Dt:
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06/06/2015
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Publication #:
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Pub Dt:
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09/24/2015
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Title:
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FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14732705
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Filing Dt:
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06/06/2015
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Publication #:
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Pub Dt:
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10/22/2015
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Title:
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BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES
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Patent #:
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Issue Dt:
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03/07/2017
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Application #:
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14732835
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Filing Dt:
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06/08/2015
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Publication #:
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Pub Dt:
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10/22/2015
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Title:
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CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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14733235
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Filing Dt:
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06/08/2015
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Publication #:
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Pub Dt:
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09/24/2015
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Title:
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SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF
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Patent #:
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Issue Dt:
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11/07/2017
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Application #:
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14733445
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Filing Dt:
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06/08/2015
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Publication #:
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Pub Dt:
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12/08/2016
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Title:
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THRU-SILICON-VIA STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14733652
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Filing Dt:
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06/08/2015
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Publication #:
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Pub Dt:
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09/24/2015
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Title:
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INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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14734018
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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09/24/2015
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Title:
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NANOPOROUS STRUCTURES BY REACTIVE ION ETCHING
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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14734310
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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10/15/2015
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Title:
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INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET
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Patent #:
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Issue Dt:
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11/22/2016
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Application #:
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14734411
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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12/15/2016
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Title:
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COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS
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Patent #:
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Issue Dt:
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03/21/2017
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Application #:
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14734504
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
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Title:
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TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE
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Patent #:
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Issue Dt:
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02/14/2017
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Application #:
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14734525
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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12/15/2016
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Title:
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CIRCUIT TO IMPROVE SRAM STABILITY
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Patent #:
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Issue Dt:
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10/11/2016
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Application #:
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14734600
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Filing Dt:
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06/09/2015
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Title:
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PASSIVATION LAYER TOPOGRAPHY
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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14734713
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Filing Dt:
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06/09/2015
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Publication #:
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Pub Dt:
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10/29/2015
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Title:
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BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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14735466
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Filing Dt:
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06/10/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14736651
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Filing Dt:
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06/11/2015
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Publication #:
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Pub Dt:
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10/01/2015
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Title:
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STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
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Patent #:
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Issue Dt:
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02/09/2016
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Application #:
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14736695
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Filing Dt:
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06/11/2015
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Publication #:
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Pub Dt:
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10/01/2015
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Title:
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STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14736698
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Filing Dt:
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06/11/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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14736942
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Filing Dt:
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06/11/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14737632
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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METHOD AND PROTECTION APPARATUS FOR PROTECTING A THERMAL SENSITIVE COMPONENT IN A THERMAL PROCESS
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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14737915
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
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Title:
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METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS
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|
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Patent #:
|
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Issue Dt:
|
06/07/2016
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Application #:
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14738025
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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TAPE SERVO TRACK WRITE COMPENSATION
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|
|
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Patent #:
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Issue Dt:
|
01/24/2017
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Application #:
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14738288
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
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Title:
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ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
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|
|
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Patent #:
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|
Issue Dt:
|
12/27/2016
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Application #:
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14738336
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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FINFET HAVING AN EPITAXIALLY GROWN SEMICONDUCTOR ON THE FIN IN THE CHANNEL REGION
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Patent #:
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Issue Dt:
|
04/24/2018
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Application #:
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14738355
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Filing Dt:
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06/12/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY
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Patent #:
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Issue Dt:
|
08/30/2016
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Application #:
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14739137
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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10/29/2015
| | | | |
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Title:
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LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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14739262
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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METHOD AND SYSTEM FOR USING A VIBRATION SIGNATURE AS AN AUTHENTICATION KEY
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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14739562
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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10/01/2015
| | | | |
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Title:
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STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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14739627
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Filing Dt:
|
06/15/2015
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Publication #:
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Pub Dt:
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10/29/2015
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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14739669
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Filing Dt:
|
06/15/2015
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|
Publication #:
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Pub Dt:
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10/01/2015
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14739686
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Filing Dt:
|
06/15/2015
|
|
Publication #:
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|
Pub Dt:
|
10/29/2015
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/03/2016
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Application #:
|
14739703
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Filing Dt:
|
06/15/2015
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|
Publication #:
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Pub Dt:
|
10/08/2015
| | | | |
|
Title:
|
MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14741169
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Filing Dt:
|
06/16/2015
|
|
Publication #:
|
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Pub Dt:
|
10/01/2015
| | | | |
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Title:
|
PRINTED TRANSISTOR AND FABRICATION METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
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Application #:
|
14741618
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Filing Dt:
|
06/17/2015
|
|
Publication #:
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|
Pub Dt:
|
10/08/2015
| | | | |
|
Title:
|
Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
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Application #:
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14741757
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Filing Dt:
|
06/17/2015
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|
Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
INDUCTION HEATING FOR UNDERFILL REMOVAL AND CHIP REWORK
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/15/2016
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Application #:
|
14741802
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Filing Dt:
|
06/17/2015
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|
Title:
|
WAFER-LEVEL CHIP-SCALE PACKAGE STRUCTURE UTILIZING CONDUCTIVE POLYMER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/02/2017
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Application #:
|
14742801
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Filing Dt:
|
06/18/2015
|
|
Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
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Title:
|
INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/16/2018
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Application #:
|
14742895
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Filing Dt:
|
06/18/2015
|
|
Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/10/2018
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Application #:
|
14742917
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Filing Dt:
|
06/18/2015
|
|
Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14743030
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Filing Dt:
|
06/18/2015
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|
Title:
|
INTEGRATED MICRO-PELTIER COOLING COMPONENTS IN SILICON-ON-INSULATOR (SOI) LAYERS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/16/2018
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Application #:
|
14743208
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Filing Dt:
|
06/18/2015
|
|
Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
DETECTING A VOID BETWEEN A VIA AND A WIRING LINE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
02/13/2018
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Application #:
|
14744198
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Filing Dt:
|
06/19/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
14744800
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Filing Dt:
|
06/19/2015
|
|
Publication #:
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|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
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LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2017
|
Application #:
|
14745547
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Filing Dt:
|
06/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
14745704
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Filing Dt:
|
06/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14745764
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Filing Dt:
|
06/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH DOUBLE-TAPERED EMITTER FINGERS
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14745800
|
Filing Dt:
|
06/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
|
Title:
|
CHIP PACKAGE WITH REDUCED TEMPERATURE VARIATION HAVING EMITTER FINGERS FORMATION ACCORDING TO THEIR PROXIMITY TO THE THERMAL PATHWAY STRUCTURE AND A METHOD FOR FORMING A SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14746017
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Filing Dt:
|
06/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/08/2015
| | | | |
|
Title:
|
SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14746891
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Filing Dt:
|
06/23/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
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ELECTRICAL FUSE WITH HIGH OFF RESISTANCE
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14747385
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Filing Dt:
|
06/23/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
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SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/15/2016
|
Application #:
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14747525
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Filing Dt:
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06/23/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
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Title:
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SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/23/2016
|
Application #:
|
14747604
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Filing Dt:
|
06/23/2015
|
|
Title:
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REPLACEMENT EMITTER FOR REDUCED CONTACT RESISTANCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2017
|
Application #:
|
14747668
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Filing Dt:
|
06/23/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
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BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2016
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Application #:
|
14748355
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Filing Dt:
|
06/24/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
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Application #:
|
14748595
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Filing Dt:
|
06/24/2015
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Publication #:
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Pub Dt:
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12/29/2016
| | | | |
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Title:
|
MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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14749731
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Filing Dt:
|
06/25/2015
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|
Publication #:
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Pub Dt:
|
11/05/2015
| | | | |
|
Title:
|
PARTITIONING OF PROGRAM ANALYSES INTO SUB-ANALYSES USING DYNAMIC HINTS
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|
|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14749750
|
Filing Dt:
|
06/25/2015
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|
Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE
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|
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|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14749772
|
Filing Dt:
|
06/25/2015
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|
Publication #:
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|
Pub Dt:
|
11/05/2015
| | | | |
|
Title:
|
Partitioning of Program Analyses into Sub-Analyses Using Dynamic Hints
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
14749809
|
Filing Dt:
|
06/25/2015
|
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED PERFORMANCE AND BREAKDOWN VOLTAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2017
|
Application #:
|
14749817
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
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Title:
|
STRUCTURE FOR BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
|
Application #:
|
14749843
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2017
|
Application #:
|
14749907
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
MULTILEVEL WAVEGUIDE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2017
|
Application #:
|
14749909
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14750476
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14750971
|
Filing Dt:
|
06/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
|
Title:
|
MANAGING METADATA FOR CACHING DEVICES DURING SHUTDOWN AND RESTART PROCEDURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2016
|
Application #:
|
14751222
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14751493
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
|
Title:
|
GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14751542
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
|
Title:
|
GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
14751557
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
FDSOI VOLTAGE REFERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14751646
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
|
Title:
|
Gate-All-Around Nanowire MOSFET and Method of Formation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14751706
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
|
Title:
|
Gate-All-Around Nanowire MOSFET and Method of Formation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14751761
|
Filing Dt:
|
06/26/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
|
Title:
|
Gate-All-Around Nanowire MOSFET and Method of Formation
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14753682
|
Filing Dt:
|
06/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
|
Title:
|
PREDICTING AND ALERTING USER TO NAVIGATION OPTIONS AND PREDICTING USER INTENTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
14753771
|
Filing Dt:
|
06/29/2015
|
|
Title:
|
DETERMINING APPROPRIATENESS OF SAMPLING INTEGRATED CIRCUIT TEST DATA IN THE PRESENCE OF MANUFACTURING VARIATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
14754013
|
Filing Dt:
|
06/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
|
Title:
|
ANALYZING COMPUTER PROGRAMS TO IDENTIFY ERRORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
14754190
|
Filing Dt:
|
06/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
|
Title:
|
METHOD FOR FABRICATING A CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
14754585
|
Filing Dt:
|
06/29/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
|
Title:
|
Copper Feature Design for Warpage Control of Substrates
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2017
|
Application #:
|
14755522
|
Filing Dt:
|
06/30/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
|
Title:
|
SWITCHABLE FILTERS AND DESIGN STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14755862
|
Filing Dt:
|
06/30/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
|
Title:
|
BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14788945
|
Filing Dt:
|
07/01/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
|
Title:
|
PLUG VIA FORMATION BY PATTERNED PLATING AND POLISHING
|
|
