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10908254
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05/04/2005
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11/03/2005
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Title:
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INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
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NONE
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09/02/2004
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03/02/2006
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Title:
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Wire sweep resistant semiconductor package and manufacturing method thereof
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NONE
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11035637
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01/14/2005
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07/20/2006
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Title:
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Under bump metallurgy in integrated circuits
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NONE
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09/24/2005
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05/18/2006
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Title:
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HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
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NONE
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11162971
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09/29/2005
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03/29/2007
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Title:
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SUBSTRATE INDEXING SYSTEM
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NONE
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11163313
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10/13/2005
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04/19/2007
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Title:
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STACKED DIE PACKAGING SYSTEM
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NONE
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11163547
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10/21/2005
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04/26/2007
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PRE-MOLDED LEADFRAME AND METHOD THEREFOR
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NONE
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11163556
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10/22/2005
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08/10/2006
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED INTERLOCKING LEADFRAME
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12/01/2009
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11164329
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11/18/2005
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03/16/2006
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INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
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NONE
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11276947
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03/17/2006
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05/17/2007
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INTEGRATED CIRCUIT PACKAGE SYSTEM
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NONE
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11278002
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03/30/2006
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10/11/2007
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
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NONE
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11279741
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04/13/2006
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05/17/2007
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM
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NONE
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11307317
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01/31/2006
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08/02/2007
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INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
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NONE
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11307349
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02/01/2006
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08/02/2007
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
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NONE
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11307498
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02/09/2006
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05/17/2007
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Title:
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STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
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NONE
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11379018
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04/17/2006
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10/18/2007
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Title:
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MULTICHIP PACKAGE SYSTEM
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09/02/2008
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11379097
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04/18/2006
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10/18/2007
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Title:
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
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03/04/2008
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11379740
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04/21/2006
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08/24/2006
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DUAL ROW LEADFRAME AND FABRICATION METHOD
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NONE
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11380587
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04/27/2006
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05/17/2007
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INTEGRATED CIRCUIT PACKAGE SYSTEM
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NONE
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11383802
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05/17/2006
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11/22/2007
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Title:
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SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
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NONE
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11388755
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03/24/2006
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09/28/2006
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Title:
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Flip chip interconnection having narrow interconnection sites on the substrate
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09/08/2015
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11420853
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05/30/2006
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11/30/2006
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Title:
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Epoxy Bump for Overhang Die
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NONE
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11435555
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05/16/2006
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11/16/2006
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Title:
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Flip chip interconnect solder mask
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NONE
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11458065
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07/17/2006
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05/17/2007
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INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
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NONE
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11469307
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08/31/2006
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01/04/2007
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Title:
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BUMP FOR OVERHANG DEVICE
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NONE
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11532508
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09/15/2006
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03/20/2008
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
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04/20/2010
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11536544
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09/28/2006
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01/25/2007
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Title:
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LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
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NONE
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11672910
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02/08/2007
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08/14/2008
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Title:
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SEMICONDUCTOR PACKAGE WIRE BONDING
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NONE
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11749712
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05/16/2007
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11/20/2008
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
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NONE
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11767820
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06/25/2007
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12/25/2008
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
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04/06/2010
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11772776
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07/02/2007
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12/06/2007
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Title:
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SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
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05/03/2016
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11857188
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09/18/2007
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03/19/2009
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
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09/11/2018
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11949282
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12/03/2007
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06/04/2009
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Wafer Level Package Integration and Method
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NONE
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12/26/2007
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07/02/2009
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Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
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NONE
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03/12/2008
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09/17/2009
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Title:
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Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
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NONE
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12055612
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03/26/2008
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10/01/2009
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
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01/12/2016
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12056402
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03/27/2008
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10/01/2009
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
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NONE
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12062403
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04/03/2008
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10/08/2009
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Title:
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Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
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NONE
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12122639
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05/16/2008
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11/19/2009
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM
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09/01/2015
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12136682
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06/10/2008
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12/10/2009
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER GROUNDED THROUGH METAL PILLARS FORMED IN PERIPHERAL REGION OF THE SEMICONDUCTOR
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03/22/2016
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07/30/2008
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02/04/2010
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Title:
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RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
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04/06/2010
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12191542
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08/14/2008
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12/04/2008
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Title:
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CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
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09/11/2012
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09/05/2008
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03/11/2010
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD OVER A HIGH-RESISTIVITY ENCAPSULANT SEPARATED FROM OTHER IPDS AND BASEBAND CIRCUIT
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01/31/2017
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09/12/2008
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03/18/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH-SILICON VIAS
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03/22/2016
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10/28/2008
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04/29/2010
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Title:
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SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
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02/09/2016
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12/10/2008
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06/10/2010
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD BENEATH A SEMICONDUCTOR DIE WITH DIRECT CONNECTION TO EXTERNAL DEVICES
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NONE
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12407949
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03/20/2009
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09/23/2010
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Title:
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Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
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NONE
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12408641
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03/20/2009
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09/23/2010
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
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NONE
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12412886
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03/27/2009
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09/30/2010
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
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05/31/2016
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06/12/2009
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12/16/2010
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Title:
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INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
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NONE
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12493049
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06/26/2009
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12/30/2010
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Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
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NONE
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12505273
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07/17/2009
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01/20/2011
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Title:
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Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
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01/05/2016
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08/17/2009
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02/17/2011
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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NONE
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12563368
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09/21/2009
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09/30/2010
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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09/15/2015
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11/13/2009
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05/19/2011
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Title:
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Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation
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05/17/2016
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01/06/2010
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04/29/2010
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Title:
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Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets
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NONE
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12688124
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01/15/2010
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05/13/2010
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Title:
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Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
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01/23/2018
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12714190
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02/26/2010
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03/24/2011
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Title:
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Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
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03/29/2016
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12714291
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02/26/2010
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09/09/2010
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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05/31/2016
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03/02/2010
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09/08/2011
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Title:
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INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH SHIELDING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12718939
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Filing Dt:
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03/05/2010
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Publication #:
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Pub Dt:
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09/08/2011
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/15/2016
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Application #:
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12722852
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Filing Dt:
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03/12/2010
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Publication #:
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Pub Dt:
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09/15/2011
| | | | |
Title:
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CARRIER SYSTEM WITH MULTI-TIER CONDUCTIVE POSTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12763378
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Filing Dt:
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04/20/2010
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Publication #:
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Pub Dt:
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08/23/2012
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Title:
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Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
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Patent #:
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Issue Dt:
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08/30/2016
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Application #:
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12773669
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Filing Dt:
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05/04/2010
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Publication #:
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Pub Dt:
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11/10/2011
| | | | |
Title:
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Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12777615
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Filing Dt:
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05/11/2010
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Publication #:
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Pub Dt:
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11/18/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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12781754
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Filing Dt:
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05/17/2010
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Publication #:
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Pub Dt:
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11/17/2011
| | | | |
Title:
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METHOD OF FORMING PERFORATED OPENING IN BOTTOM SUBSTRATE OF FLIPCHIP POP ASSEMBLY TO REDUCE BLEEDING OF UNDERFILL MATERIAL
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12782164
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Filing Dt:
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05/18/2010
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Publication #:
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Pub Dt:
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10/13/2011
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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12786008
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05/24/2010
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Publication #:
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Pub Dt:
|
11/24/2011
| | | | |
Title:
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Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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12813335
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Filing Dt:
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06/10/2010
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Publication #:
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Pub Dt:
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09/30/2010
| | | | |
Title:
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Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12819162
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Filing Dt:
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06/18/2010
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Publication #:
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Pub Dt:
|
12/22/2011
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12837562
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Filing Dt:
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07/16/2010
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Publication #:
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Pub Dt:
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01/19/2012
| | | | |
Title:
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Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
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Patent #:
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Issue Dt:
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03/08/2016
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Application #:
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12882728
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Filing Dt:
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09/15/2010
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Publication #:
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Pub Dt:
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01/06/2011
| | | | |
Title:
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Chip Scale Module Package in BGA Semiconductor Package
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12882748
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Filing Dt:
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09/15/2010
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Publication #:
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Pub Dt:
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02/03/2011
| | | | |
Title:
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Stackable Package By Using Internal Stacking Modules
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12946841
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Filing Dt:
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11/15/2010
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/20/2019
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Application #:
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12947414
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Filing Dt:
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11/16/2010
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING FLIPCHIP INTERCONNECT STRUCTURE
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Patent #:
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02/09/2016
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Application #:
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12961107
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Filing Dt:
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12/06/2010
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Publication #:
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Pub Dt:
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08/16/2012
| | | | |
Title:
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Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
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Patent #:
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05/17/2016
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Application #:
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12969451
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Filing Dt:
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12/15/2010
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Publication #:
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Pub Dt:
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12/15/2011
| | | | |
Title:
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Semiconductor Device and Method of Forming Flipchip Interconnection Structure with Bump on Partial Pad
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Patent #:
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Issue Dt:
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09/08/2015
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Application #:
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12985559
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
|
05/05/2011
| | | | |
Title:
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Semiconductor Device with Bump Interconnection
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13038384
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Filing Dt:
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03/01/2011
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Publication #:
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Pub Dt:
|
09/06/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13038843
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Filing Dt:
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03/02/2011
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Publication #:
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Pub Dt:
|
08/30/2012
| | | | |
Title:
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Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13039309
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Filing Dt:
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03/28/2018
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Publication #:
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Pub Dt:
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09/06/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13042457
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Filing Dt:
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03/07/2011
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Publication #:
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Pub Dt:
|
09/13/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13070362
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Filing Dt:
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03/23/2011
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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NONE
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Application #:
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13098419
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Filing Dt:
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04/30/2011
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Publication #:
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Pub Dt:
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08/25/2011
| | | | |
Title:
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Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame
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Patent #:
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Issue Dt:
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10/04/2016
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13172680
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Filing Dt:
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06/29/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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Semiconductor Device and Method of Wafer Level Package Integration
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Patent #:
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Issue Dt:
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06/02/2015
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Application #:
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13190339
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Filing Dt:
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07/25/2011
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
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Patent #:
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Issue Dt:
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07/14/2015
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13191318
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07/26/2011
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
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Patent #:
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NONE
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Application #:
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13209837
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Filing Dt:
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08/15/2011
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
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04/19/2016
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13211303
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08/16/2011
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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12/16/2014
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13231789
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09/13/2011
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Pub Dt:
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01/05/2012
| | | | |
Title:
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Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
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Patent #:
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12/30/2014
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13235413
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09/18/2011
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Publication #:
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Pub Dt:
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01/05/2012
| | | | |
Title:
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Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
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Issue Dt:
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11/06/2012
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13237828
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09/20/2011
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01/12/2012
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Title:
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SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
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01/12/2016
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13242306
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09/23/2011
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Pub Dt:
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03/28/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
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12/27/2016
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13243474
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09/23/2011
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Pub Dt:
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03/28/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF
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NONE
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14341578
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07/25/2014
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Pub Dt:
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11/13/2014
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
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NONE
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14565731
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12/10/2014
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Pub Dt:
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05/21/2015
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Title:
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Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
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Patent #:
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Issue Dt:
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07/26/2016
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Application #:
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14600825
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Filing Dt:
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01/20/2015
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Publication #:
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Pub Dt:
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05/21/2015
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV
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Patent #:
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Issue Dt:
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09/25/2018
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14637054
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03/03/2015
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
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Patent #:
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Issue Dt:
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06/28/2016
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Application #:
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14682914
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Filing Dt:
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04/09/2015
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
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