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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:061593/0094   Pages: 13
Recorded: 10/03/2022
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 81
1
Patent #:
5790138
Issue Dt:
08/04/1998
Application #:
08587379
Filing Dt:
01/16/1996
Title:
METHOD AND STRUCTURE FOR IMPROVING DISPLAY DATA BANDWIDTH IN A UNIFIED MEMORY ARCHITECTURE SYSTEM
2
Patent #:
5923593
Issue Dt:
07/13/1999
Application #:
08767707
Filing Dt:
12/17/1996
Title:
MULTI-PORT DRAM CELL AND MEMORY SYSTEM USING SAME
3
Patent #:
6075720
Issue Dt:
06/13/2000
Application #:
09134488
Filing Dt:
08/14/1998
Title:
MEMORY CELL FOR DRAM EMBEDDED IN LOGIC
4
Patent #:
5999474
Issue Dt:
12/07/1999
Application #:
09165228
Filing Dt:
10/01/1998
Title:
METHOD AND APPARATUS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY
5
Patent #:
6075740
Issue Dt:
06/13/2000
Application #:
09181840
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICES
6
Patent #:
6415353
Issue Dt:
07/02/2002
Application #:
09405607
Filing Dt:
09/24/1999
Title:
READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME
7
Patent #:
6457108
Issue Dt:
09/24/2002
Application #:
09415032
Filing Dt:
10/07/1999
Title:
METHOD OF OPERATING A SYSTEM-ON-A-CHIP INCLUDING ENTERING A STANDBY STATE IN A NON-VOLATILE MEMORY WHILE OPERATING THE SYSTEM-ON-A-CHIP FROM A VOLATILE MEMORY
8
Patent #:
6732229
Issue Dt:
05/04/2004
Application #:
09503751
Filing Dt:
02/14/2000
Title:
METHOD AND APPARATUS FOR MEMORY REDUNDANCY WITH NO CRITICAL DELAY-PATH
9
Patent #:
6256248
Issue Dt:
07/03/2001
Application #:
09590943
Filing Dt:
06/09/2000
Title:
Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices
10
Patent #:
6496437
Issue Dt:
12/17/2002
Application #:
09795750
Filing Dt:
02/27/2001
Publication #:
US20010008496
Pub Dt:
07/19/2001
Title:
METHOD AND APPARATUS FOR FORCING IDLE CYCLES TO ENABLE REFRESH OPERATIONS IN A SEMICONDUCTOR MEMORY
11
Patent #:
7051264
Issue Dt:
05/23/2006
Application #:
10003602
Filing Dt:
11/14/2001
Publication #:
US20030093744
Pub Dt:
05/15/2003
Title:
ERROR CORRECTING MEMORY AND METHOD OF OPERATING SAME
12
Patent #:
6573548
Issue Dt:
06/03/2003
Application #:
10033690
Filing Dt:
11/02/2001
Publication #:
US20020094697
Pub Dt:
07/18/2002
Title:
DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
13
Patent #:
6584036
Issue Dt:
06/24/2003
Application #:
10096945
Filing Dt:
03/14/2002
Publication #:
US20020131320
Pub Dt:
09/19/2002
Title:
SRAM EMULATOR
14
Patent #:
6784048
Issue Dt:
08/31/2004
Application #:
10231800
Filing Dt:
08/28/2002
Publication #:
US20030001181
Pub Dt:
01/02/2003
Title:
METHOD OF FABRICATING A DRAM CELL HAVING A THIN DIELECTRIC ACCESS TRANSISTOR AND A THICK DIELECTRIC STORAGE CAPACITOR
15
Patent #:
6841821
Issue Dt:
01/11/2005
Application #:
10355477
Filing Dt:
01/31/2003
Publication #:
US20030147277
Pub Dt:
08/07/2003
Title:
NON-VOLATILE MEMORY CELL FABRICATED WITH SLIGHT MODIFICATION TO A CONVENTIONAL LOGIC PROCESS AND METHODS OF OPERATING SAME
16
Patent #:
6642098
Issue Dt:
11/04/2003
Application #:
10374917
Filing Dt:
02/25/2003
Publication #:
US20030151071
Pub Dt:
08/14/2003
Title:
DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
17
Patent #:
6826069
Issue Dt:
11/30/2004
Application #:
10737825
Filing Dt:
12/18/2003
Publication #:
US20040125636
Pub Dt:
07/01/2004
Title:
INTERLEAVED WORDLINE ARCHITECTURE
18
Patent #:
7167410
Issue Dt:
01/23/2007
Application #:
11114807
Filing Dt:
04/26/2005
Publication #:
US20060239107
Pub Dt:
10/26/2006
Title:
MEMORY SYSTEM AND MEMORY DEVICE HAVING A SERIAL INTERFACE
19
Patent #:
7599396
Issue Dt:
10/06/2009
Application #:
11178958
Filing Dt:
07/11/2005
Publication #:
US20070008992
Pub Dt:
01/11/2007
Title:
METHOD OF ENCODING AND SYNCHRONIZING A SERIAL INTERFACE
20
Patent #:
7352307
Issue Dt:
04/01/2008
Application #:
11351877
Filing Dt:
02/09/2006
Publication #:
US20070182606
Pub Dt:
08/09/2007
Title:
COMPARATOR CHAIN OFFSET REDUCTION
21
Patent #:
7382658
Issue Dt:
06/03/2008
Application #:
11421986
Filing Dt:
06/02/2006
Publication #:
US20070279987
Pub Dt:
12/06/2007
Title:
NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
22
Patent #:
7533222
Issue Dt:
05/12/2009
Application #:
11427785
Filing Dt:
06/29/2006
Publication #:
US20080005492
Pub Dt:
01/03/2008
Title:
DUAL-PORT SRAM MEMORY USING SINGLE-PORT MEMORY CELL
23
Patent #:
7499307
Issue Dt:
03/03/2009
Application #:
11534506
Filing Dt:
09/22/2006
Publication #:
US20070070759
Pub Dt:
03/29/2007
Title:
SCALABLE EMBEDDED DRAM ARRAY
24
Patent #:
7447104
Issue Dt:
11/04/2008
Application #:
11559870
Filing Dt:
11/14/2006
Publication #:
US20070109906
Pub Dt:
05/17/2007
Title:
WORD LINE DRIVER FOR DRAM EMBEDDED IN A LOGIC PROCESS
25
Patent #:
7919367
Issue Dt:
04/05/2011
Application #:
12021229
Filing Dt:
01/28/2008
Publication #:
US20080138950
Pub Dt:
06/12/2008
Title:
METHOD TO INCREASE CHARGE RETENTION OF NON-VOLATILE MEMORY MANUFACTURED IN A SINGLE-GATE LOGIC PROCESS
26
Patent #:
7477546
Issue Dt:
01/13/2009
Application #:
12021255
Filing Dt:
01/28/2008
Publication #:
US20080137437
Pub Dt:
06/12/2008
Title:
NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
27
Patent #:
7728747
Issue Dt:
06/01/2010
Application #:
12041578
Filing Dt:
03/03/2008
Publication #:
US20080211702
Pub Dt:
09/04/2008
Title:
COMPARATOR CHAIN OFFSET REDUCTION
28
Patent #:
7791975
Issue Dt:
09/07/2010
Application #:
12048170
Filing Dt:
03/13/2008
Publication #:
US20080159036
Pub Dt:
07/03/2008
Title:
SCALABLE EMBEDDED DRAM ARRAY
29
Patent #:
7929359
Issue Dt:
04/19/2011
Application #:
12291762
Filing Dt:
11/13/2008
Publication #:
US20100118596
Pub Dt:
05/13/2010
Title:
EMBEDDED DRAM WITH BIAS-INDEPENDENT CAPACITANCE
30
Patent #:
8361863
Issue Dt:
01/29/2013
Application #:
12291765
Filing Dt:
11/13/2008
Publication #:
US20100120213
Pub Dt:
05/13/2010
Title:
EMBEDDED DRAM WITH MULTIPLE GATE OXIDE THICKNESSES
31
Patent #:
7894270
Issue Dt:
02/22/2011
Application #:
12378248
Filing Dt:
02/11/2009
Publication #:
US20100202203
Pub Dt:
08/12/2010
Title:
DATA RESTORATION METHOD FOR A NON-VOLATILE MEMORY
32
Patent #:
8161355
Issue Dt:
04/17/2012
Application #:
12378249
Filing Dt:
02/11/2009
Publication #:
US20100205504
Pub Dt:
08/12/2010
Title:
AUTOMATIC REFRESH FOR IMPROVING DATA RETENTION AND ENDURANCE CHARACTERISTICS OF AN EMBEDDED NON-VOLATILE MEMORY IN A STANDARD CMOS LOGIC PROCESS
33
Patent #:
8171234
Issue Dt:
05/01/2012
Application #:
12404955
Filing Dt:
03/16/2009
Publication #:
US20100235590
Pub Dt:
09/16/2010
Title:
MULTI-BANK MULTI-PORT ARCHITECTURE
34
Patent #:
8044724
Issue Dt:
10/25/2011
Application #:
12430430
Filing Dt:
04/27/2009
Publication #:
US20100073051
Pub Dt:
03/25/2010
Title:
LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS
35
Patent #:
8135037
Issue Dt:
03/13/2012
Application #:
12548135
Filing Dt:
08/26/2009
Publication #:
US20090316728
Pub Dt:
12/24/2009
Title:
METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE
36
Patent #:
8139399
Issue Dt:
03/20/2012
Application #:
12577994
Filing Dt:
10/13/2009
Publication #:
US20110085398
Pub Dt:
04/14/2011
Title:
MULTIPLE CYCLE MEMORY WRITE COMPLETION
37
Patent #:
8526265
Issue Dt:
09/03/2013
Application #:
12645321
Filing Dt:
12/22/2009
Publication #:
US20110149673
Pub Dt:
06/23/2011
Title:
THREE STATE WORD LINE DRIVER FOR A DRAM MEMORY DEVICE
38
Patent #:
8539196
Issue Dt:
09/17/2013
Application #:
12697132
Filing Dt:
01/29/2010
Publication #:
US20110191564
Pub Dt:
08/04/2011
Title:
Hierarchical Organization Of Large Memory Blocks
39
Patent #:
9342471
Issue Dt:
05/17/2016
Application #:
12697141
Filing Dt:
01/29/2010
Publication #:
US20110191548
Pub Dt:
08/04/2011
Title:
High Utilization Multi-Partitioned Serial Memory
40
Patent #:
8547774
Issue Dt:
10/01/2013
Application #:
12697150
Filing Dt:
01/29/2010
Publication #:
US20110188335
Pub Dt:
08/04/2011
Title:
HIERARCHICAL MULTI-BANK MULTI-PORT MEMORY ORGANIZATION
41
Patent #:
8832336
Issue Dt:
09/09/2014
Application #:
12697223
Filing Dt:
01/30/2010
Publication #:
US20110191619
Pub Dt:
08/04/2011
Title:
Reducing Latency in Serializer-Deserializer Links
42
Patent #:
8370725
Issue Dt:
02/05/2013
Application #:
12697763
Filing Dt:
02/01/2010
Publication #:
US20110191647
Pub Dt:
08/04/2011
Title:
COMMUNICATION INTERFACE AND PROTOCOL
43
Patent #:
8266471
Issue Dt:
09/11/2012
Application #:
12702767
Filing Dt:
02/09/2010
Publication #:
US20110197087
Pub Dt:
08/11/2011
Title:
MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT
44
Patent #:
8269538
Issue Dt:
09/18/2012
Application #:
12768513
Filing Dt:
04/27/2010
Publication #:
US20100271094
Pub Dt:
10/28/2010
Title:
SIGNAL ALIGNMENT SYSTEM
45
Patent #:
8460995
Issue Dt:
06/11/2013
Application #:
12804855
Filing Dt:
07/30/2010
Publication #:
US20120025347
Pub Dt:
02/02/2012
Title:
Method of forming a MIM capacitor
46
Patent #:
8901747
Issue Dt:
12/02/2014
Application #:
12846763
Filing Dt:
07/29/2010
Publication #:
US20120025397
Pub Dt:
02/02/2012
Title:
SEMICONDUCTOR CHIP LAYOUT
47
Patent #:
8436660
Issue Dt:
05/07/2013
Application #:
12870549
Filing Dt:
08/27/2010
Publication #:
US20120054704
Pub Dt:
03/01/2012
Title:
VOLTAGE-MODE DRIVER WITH EQUALIZATION
48
Patent #:
8274326
Issue Dt:
09/25/2012
Application #:
12872852
Filing Dt:
08/31/2010
Publication #:
US20120049946
Pub Dt:
03/01/2012
Title:
EQUALIZATION CIRCUIT
49
Patent #:
8217814
Issue Dt:
07/10/2012
Application #:
12971847
Filing Dt:
12/17/2010
Publication #:
US20120154186
Pub Dt:
06/21/2012
Title:
LOW POWER SERIAL TO PARALLEL CONVERTER
50
Patent #:
8238169
Issue Dt:
08/07/2012
Application #:
13027621
Filing Dt:
02/15/2011
Publication #:
US20110141812
Pub Dt:
06/16/2011
Title:
METHOD AND APPARATUS FOR RESTORING DATA IN A NON-VOLATILE MEMORY
51
Patent #:
8954803
Issue Dt:
02/10/2015
Application #:
13030358
Filing Dt:
02/18/2011
Publication #:
US20110209002
Pub Dt:
08/25/2011
Title:
PROGRAMMABLE TEST ENGINE (PCDTE) FOR EMERGING MEMORY TECHNOLOGIES
52
Patent #:
8473695
Issue Dt:
06/25/2013
Application #:
13077261
Filing Dt:
03/31/2011
Publication #:
US20120254562
Pub Dt:
10/04/2012
Title:
MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING
53
Patent #:
8681574
Issue Dt:
03/25/2014
Application #:
13077798
Filing Dt:
03/31/2011
Publication #:
US20120250441
Pub Dt:
10/04/2012
Title:
SEPARATE PASS GATE CONTROLLED SENSE AMPLIFIER
54
Patent #:
8451675
Issue Dt:
05/28/2013
Application #:
13077811
Filing Dt:
03/31/2011
Publication #:
US20120250442
Pub Dt:
10/04/2012
Title:
METHODS FOR ACCESSING DRAM CELLS USING SEPARATE BIT LINE CONTROL
55
Patent #:
8587046
Issue Dt:
11/19/2013
Application #:
13191423
Filing Dt:
07/26/2011
Publication #:
US20120025285
Pub Dt:
02/02/2012
Title:
SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR
56
Patent #:
9118611
Issue Dt:
08/25/2015
Application #:
13215205
Filing Dt:
08/22/2011
Publication #:
US20120047260
Pub Dt:
02/23/2012
Title:
Data Synchronization For Circuit Resources Without Using A Resource Buffer
57
Patent #:
8446755
Issue Dt:
05/21/2013
Application #:
13369253
Filing Dt:
02/08/2012
Publication #:
US20120140581
Pub Dt:
06/07/2012
Title:
MULTIPLE CYCLE MEMORY WRITE COMPLETION
58
Patent #:
8527676
Issue Dt:
09/03/2013
Application #:
13467955
Filing Dt:
05/09/2012
Publication #:
US20120221882
Pub Dt:
08/30/2012
Title:
REDUCING LATENCY IN SERIALIZER-DESERIALIZER LINKS
59
Patent #:
8635417
Issue Dt:
01/21/2014
Application #:
13468850
Filing Dt:
05/10/2012
Publication #:
US20120254558
Pub Dt:
10/04/2012
Title:
MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING
60
Patent #:
8368217
Issue Dt:
02/05/2013
Application #:
13541658
Filing Dt:
07/03/2012
Publication #:
US20120267769
Pub Dt:
10/25/2012
Title:
INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS
61
Patent #:
8704570
Issue Dt:
04/22/2014
Application #:
13720981
Filing Dt:
12/19/2012
Publication #:
US20130154698
Pub Dt:
06/20/2013
Title:
DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT
62
Patent #:
10320370
Issue Dt:
06/11/2019
Application #:
13728910
Filing Dt:
12/27/2012
Publication #:
US20130169314
Pub Dt:
07/04/2013
Title:
METHODS AND CIRCUITS FOR ADJUSTING PARAMETERS OF A TRANSCEIVER
63
Patent #:
9037928
Issue Dt:
05/19/2015
Application #:
13732783
Filing Dt:
01/02/2013
Publication #:
US20130173970
Pub Dt:
07/04/2013
Title:
MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR
64
Patent #:
8836381
Issue Dt:
09/16/2014
Application #:
13787692
Filing Dt:
03/06/2013
Publication #:
US20130342241
Pub Dt:
12/26/2013
Title:
Pseudo-Supply Hybrid Driver
65
Patent #:
8988956
Issue Dt:
03/24/2015
Application #:
13834856
Filing Dt:
03/15/2013
Publication #:
US20140078841
Pub Dt:
03/20/2014
Title:
PROGRAMMABLE MEMORY BUILT IN SELF REPAIR CIRCUIT
66
Patent #:
NONE
Issue Dt:
Application #:
13838971
Filing Dt:
03/15/2013
Publication #:
US20130329553
Pub Dt:
12/12/2013
Title:
TRAFFIC METERING AND SHAPING FOR NETWORK PACKETS
67
Patent #:
9496009
Issue Dt:
11/15/2016
Application #:
13841025
Filing Dt:
03/15/2013
Publication #:
US20130332665
Pub Dt:
12/12/2013
Title:
MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE
68
Patent #:
8890332
Issue Dt:
11/18/2014
Application #:
13843427
Filing Dt:
03/15/2013
Publication #:
US20130313723
Pub Dt:
11/28/2013
Title:
SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINES
69
Patent #:
9354823
Issue Dt:
05/31/2016
Application #:
13911218
Filing Dt:
06/06/2013
Publication #:
US20130332681
Pub Dt:
12/12/2013
Title:
MEMORY SYSTEM INCLUDING VARIABLE WRITE BURST AND BROADCAST COMMAND SCHEDULING
70
Patent #:
NONE
Issue Dt:
Application #:
13911999
Filing Dt:
06/06/2013
Publication #:
US20130329555
Pub Dt:
12/12/2013
Title:
DUAL COUNTER
71
Patent #:
9667546
Issue Dt:
05/30/2017
Application #:
13912033
Filing Dt:
06/06/2013
Publication #:
US20130332708
Pub Dt:
12/12/2013
Title:
PROGRAMMABLE PARTITIONABLE COUNTER
72
Patent #:
9054578
Issue Dt:
06/09/2015
Application #:
13923160
Filing Dt:
06/20/2013
Publication #:
US20130342242
Pub Dt:
12/26/2013
Title:
HYBRID DRIVER INCLUDING A TURBO MODE
73
Patent #:
9030894
Issue Dt:
05/12/2015
Application #:
13972798
Filing Dt:
08/21/2013
Publication #:
US20130336074
Pub Dt:
12/19/2013
Title:
HIERARCHICAL MULTI-BANK MULTI-PORT MEMORY ORGANIZATION
74
Patent #:
11119857
Issue Dt:
09/14/2021
Application #:
14031031
Filing Dt:
09/18/2013
Publication #:
US20140082453
Pub Dt:
03/20/2014
Title:
SUBSTITUTE REDUNDANT MEMORY
75
Patent #:
NONE
Issue Dt:
Application #:
14231730
Filing Dt:
03/31/2014
Publication #:
US20150244381
Pub Dt:
08/27/2015
Title:
DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE
76
Patent #:
9148154
Issue Dt:
09/29/2015
Application #:
14231739
Filing Dt:
03/31/2014
Publication #:
US20150263737
Pub Dt:
09/17/2015
Title:
DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS
77
Patent #:
9361196
Issue Dt:
06/07/2016
Application #:
14320632
Filing Dt:
06/30/2014
Publication #:
US20140317460
Pub Dt:
10/23/2014
Title:
MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING
78
Patent #:
9553566
Issue Dt:
01/24/2017
Application #:
14564618
Filing Dt:
12/09/2014
Publication #:
US20160164498
Pub Dt:
06/09/2016
Title:
HYBRID DRIVER CIRCUIT
79
Patent #:
9529569
Issue Dt:
12/27/2016
Application #:
14839576
Filing Dt:
08/28/2015
Publication #:
US20160019029
Pub Dt:
01/21/2016
Title:
Method and Apparatus for Randomizer
80
Patent #:
NONE
Issue Dt:
Application #:
14872002
Filing Dt:
09/30/2015
Publication #:
US20160188222
Pub Dt:
06/30/2016
Title:
Integrated Main Memory And Coprocessor With Low Latency
81
Patent #:
9921755
Issue Dt:
03/20/2018
Application #:
14872137
Filing Dt:
09/30/2015
Publication #:
US20160188481
Pub Dt:
06/30/2016
Title:
INTEGRATED MAIN MEMORY AND COPROCESSOR WITH LOW LATENCY
Assignor
1
PERASO INC. F/K/A MOSYS, INC.
Exec Dt:
10/03/2022
Assignee
1
INGALLS & SNYDER LLC
1325 AVENUE OF THE AMERICAS
18TH FLOOR
NEW YORK, NEW YORK 10019
Correspondence name and address
NICHOLAS NIETO
437 MADISON AVE
25TH FLOOR
NEW YORK, NY 10022

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