Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 041198/0095 | |
| Pages: | 4 |
| | Recorded: | 02/07/2017 | | |
| Attorney Dkt #: | 112689-0001-102 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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11/07/2017
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Application #:
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15199934
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Filing Dt:
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06/30/2016
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Publication #:
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Pub Dt:
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08/10/2017
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Title:
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METHODS AND SYSTEMS FOR REDUCING ELECTRICAL DISTURB EFFECTS BETWEEN THYRISTOR MEMORY CELLS USING BURIED METAL CATHODE LINES
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Assignee
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| 137 CHAPMAN ROAD |
| WOODSIDE, CALIFORNIA 94062 |
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Correspondence name and address
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ROPES & GRAY LLP
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1900 UNIVERSITY AVENUE
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6TH FLOOR
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EAST PALO ALTO, CA 94303-2284
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