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Reel/Frame:	041675/0105			Pages:	31
		Recorded:	02/10/2017
Attorney Dkt #:	065664/0012
Conveyance:	SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT

Total properties: 303
Page 2 of 4
Pages: 1 2 3 4

Patent #:	9496358	Issue Dt:	11/15/2016	Application #:	14289936	Filing Dt:	05/29/2014
Publication #:	US20150349072	Pub Dt:	12/03/2015
Title:	SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

Patent #:	NONE	Issue Dt:		Application #:	14290987	Filing Dt:	05/30/2014
Publication #:	US20150348963	Pub Dt:	12/03/2015
Title:	CYLINDER-SHAPED STORAGE NODE WITH SINGLE-LAYER SUPPORTING STRUCTURE

Patent #:	9000532	Issue Dt:	04/07/2015	Application #:	14316972	Filing Dt:	06/27/2014
Publication #:	US20140306269	Pub Dt:	10/16/2014
Title:	VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

Patent #:	9360401	Issue Dt:	06/07/2016	Application #:	14495864	Filing Dt:	09/24/2014
Publication #:	US20160084742	Pub Dt:	03/24/2016
Title:	SAMPLE STACK STRUCTURE AND METHOD FOR PREPARING THE SAME

Patent #:	9257553	Issue Dt:	02/09/2016	Application #:	14504385	Filing Dt:	10/01/2014
Publication #:	US20150349118	Pub Dt:	12/03/2015
Title:	VERTICAL TRANSISTOR AND METHOD TO FORM VERTICAL TRANSISTOR CONTACT NODE

Patent #:	9171847	Issue Dt:	10/27/2015	Application #:	14505490	Filing Dt:	10/02/2014
Title:	SEMICONDUCTOR STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14509151	Filing Dt:	10/08/2014
Publication #:	US20160104782	Pub Dt:	04/14/2016
Title:	TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Patent #:	9397048	Issue Dt:	07/19/2016	Application #:	14664932	Filing Dt:	03/23/2015
Title:	SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Patent #:	9465048	Issue Dt:	10/11/2016	Application #:	14667676	Filing Dt:	03/24/2015
Publication #:	US20160282385	Pub Dt:	09/29/2016
Title:	PROBE UNIT FOR TEST TOOLS AND METHOD OF MANUFACTURING THE SAME

Patent #:	9466713	Issue Dt:	10/11/2016	Application #:	14702771	Filing Dt:	05/04/2015
Publication #:	US20160093732	Pub Dt:	03/31/2016
Title:	NON-FLOATING VERTICAL TRANSISTOR STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14714334	Filing Dt:	05/17/2015
Publication #:	US20160336413	Pub Dt:	11/17/2016
Title:	RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE

Patent #:	9401326	Issue Dt:	07/26/2016	Application #:	14720830	Filing Dt:	05/24/2015
Title:	SPLIT CONTACT STRUCTURE AND FABRICATION METHOD THEREOF

Patent #:	9455243	Issue Dt:	09/27/2016	Application #:	14720840	Filing Dt:	05/25/2015
Title:	SILICON INTERPOSER AND FABRICATION METHOD THEREOF

Patent #:	10043769	Issue Dt:	08/07/2018	Application #:	14730231	Filing Dt:	06/03/2015
Publication #:	US20160358865	Pub Dt:	12/08/2016
Title:	SEMICONDUCTOR DEVICES INCLUDING DUMMY CHIPS

Patent #:	9916999	Issue Dt:	03/13/2018	Application #:	14731380	Filing Dt:	06/04/2015
Publication #:	US20160358847	Pub Dt:	12/08/2016
Title:	METHODS OF FABRICATING A SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING AT LEAST ONE REDISTRIBUTION LAYER

Patent #:	10373922	Issue Dt:	08/06/2019	Application #:	14731382	Filing Dt:	06/04/2015
Publication #:	US20160358870	Pub Dt:	12/08/2016
Title:	METHODS OF MANUFACTURING A MULTI-DEVICE PACKAGE

Patent #:	10008461	Issue Dt:	06/26/2018	Application #:	14731426	Filing Dt:	06/05/2015
Publication #:	US20160358868	Pub Dt:	12/08/2016
Title:	SEMICONDUCTOR STRUCTURE HAVING A PATTERNED SURFACE STRUCTURE AND SEMICONDUCTOR CHIPS INCLUDING SUCH STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14735127	Filing Dt:	06/09/2015
Publication #:	US20160365334	Pub Dt:	12/15/2016
Title:	PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

Patent #:	9768175	Issue Dt:	09/19/2017	Application #:	14745464	Filing Dt:	06/21/2015
Publication #:	US20160372475	Pub Dt:	12/22/2016
Title:	SEMICONDUCTOR DEVICES COMPRISING GATE STRUCTURE SIDEWALLS HAVING DIFFERENT ANGLES

Patent #:	9520333	Issue Dt:	12/13/2016	Application #:	14745473	Filing Dt:	06/22/2015
Publication #:	US20160372395	Pub Dt:	12/22/2016
Title:	WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

Patent #:	9472664	Issue Dt:	10/18/2016	Application #:	14803100	Filing Dt:	07/19/2015
Title:	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Patent #:	9449935	Issue Dt:	09/20/2016	Application #:	14810415	Filing Dt:	07/27/2015
Title:	WAFER LEVEL PACKAGE HAVING REDISTRIBUTION LAYER AND FABRICATION METHOD THEREOF

Patent #:	9870934	Issue Dt:	01/16/2018	Application #:	14810492	Filing Dt:	07/28/2015
Publication #:	US20170032989	Pub Dt:	02/02/2017
Title:	ELECTROSTATIC CHUCK AND TEMPERATURE-CONTROL METHOD FOR THE SAME

Patent #:	9543270	Issue Dt:	01/10/2017	Application #:	14814524	Filing Dt:	07/31/2015
Publication #:	US20170033078	Pub Dt:	02/02/2017
Title:	MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Patent #:	9930264	Issue Dt:	03/27/2018	Application #:	14837802	Filing Dt:	08/27/2015
Publication #:	US20150365579	Pub Dt:	12/17/2015
Title:	METHOD AND APPARATUS PROVIDING PIXEL ARRAY HAVING AUTOMATIC LIGHT CONTROL PIXELS AND IMAGE CAPTURE PIXELS

Patent #:	9735161	Issue Dt:	08/15/2017	Application #:	14848357	Filing Dt:	09/09/2015
Publication #:	US20170069632	Pub Dt:	03/09/2017
Title:	MEMORY DEVICE AND FABRICATING METHOD THEREOF

Patent #:	9864879	Issue Dt:	01/09/2018	Application #:	14876600	Filing Dt:	10/06/2015
Publication #:	US20170098102	Pub Dt:	04/06/2017
Title:	SECURE SUBSYSTEM

Patent #:	9379197	Issue Dt:	06/28/2016	Application #:	14877889	Filing Dt:	10/07/2015
Title:	RECESS ARRAY DEVICE

Patent #:	9449953	Issue Dt:	09/20/2016	Application #:	14877949	Filing Dt:	10/08/2015
Title:	PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

Patent #:	9748184	Issue Dt:	08/29/2017	Application #:	14883632	Filing Dt:	10/15/2015
Publication #:	US20170110419	Pub Dt:	04/20/2017
Title:	WAFER LEVEL PACKAGE WITH TSV-LESS INTERPOSER

Patent #:	10056338	Issue Dt:	08/21/2018	Application #:	14923449	Filing Dt:	10/27/2015
Publication #:	US20170117232	Pub Dt:	04/27/2017
Title:	METHODS OF FORMING SEMICONDUCTOR PACKAGES INCLUDING MOLDING SEMICONDUCTOR CHIPS OF THE SEMICONDUCTOR PACKAGES

Patent #:	9761540	Issue Dt:	09/12/2017	Application #:	14927491	Filing Dt:	10/30/2015
Publication #:	US20160379935	Pub Dt:	12/29/2016
Title:	WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

Patent #:	10121849	Issue Dt:	11/06/2018	Application #:	14941665	Filing Dt:	11/16/2015
Publication #:	US20170141185	Pub Dt:	05/18/2017
Title:	METHODS OF FABRICATING A SEMICONDUCTOR STRUCTURE

Patent #:	9784788	Issue Dt:	10/10/2017	Application #:	14953025	Filing Dt:	11/27/2015
Publication #:	US20170153289	Pub Dt:	06/01/2017
Title:	FAULT ISOLATION SYSTEM AND METHOD FOR DETECTING FAULTS IN A CIRCUIT

Patent #:	9607967	Issue Dt:	03/28/2017	Application #:	14977645	Filing Dt:	12/22/2015
Title:	MULTI-CHIP SEMICONDUCTOR PACKAGE WITH VIA COMPONENTS AND METHOD FOR MANUFACTURING THE SAME

Patent #:	NONE	Issue Dt:		Application #:	14986729	Filing Dt:	01/04/2016
Publication #:	US20170194181	Pub Dt:	07/06/2017
Title:	OVERHEAD TRAVELING VEHICLE, TRANSPORTATION SYSTEM WITH THE SAME, AND METHOD OF OPERATING THE SAME

Patent #:	9576933	Issue Dt:	02/21/2017	Application #:	14989782	Filing Dt:	01/06/2016
Title:	FAN-OUT WAFER LEVEL PACKAGING AND MANUFACTURING METHOD THEREOF

Patent #:	9704872	Issue Dt:	07/11/2017	Application #:	14990776	Filing Dt:	01/07/2016
Publication #:	US20170200724	Pub Dt:	07/13/2017
Title:	MEMORY DEVICE AND FABRICATING METHOD THEREOF

Patent #:	9865516	Issue Dt:	01/09/2018	Application #:	14992013	Filing Dt:	01/10/2016
Publication #:	US20170200661	Pub Dt:	07/13/2017
Title:	WAFERS HAVING A DIE REGION AND A SCRIBE-LINE REGION ADJACENT TO THE DIE REGION

Patent #:	10388564	Issue Dt:	08/20/2019	Application #:	14993099	Filing Dt:	01/12/2016
Publication #:	US20170200722	Pub Dt:	07/13/2017
Title:	METHOD FOR FABRICATING A MEMORY DEVICE HAVING TWO CONTACTS

Patent #:	9419001	Issue Dt:	08/16/2016	Application #:	14996240	Filing Dt:	01/15/2016
Title:	METHOD FOR FORMING CELL CONTACT

Patent #:	10121734	Issue Dt:	11/06/2018	Application #:	15001255	Filing Dt:	01/20/2016
Publication #:	US20170207154	Pub Dt:	07/20/2017
Title:	SEMICONDUCTOR DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15001267	Filing Dt:	01/20/2016
Publication #:	US20170205712	Pub Dt:	07/20/2017
Title:	DEVELOPMENT APPARATUS AND METHOD FOR DEVELOPING PHOTORESIST LAYER ON WAFER USING THE SAME

Patent #:	9859284	Issue Dt:	01/02/2018	Application #:	15002401	Filing Dt:	01/21/2016
Publication #:	US20170213834	Pub Dt:	07/27/2017
Title:	SEMICONDUCTOR MEMORY DEVICE HAVING ENLARGED CELL CONTACT AREA AND METHOD OF FABRICATING THE SAME

Patent #:	9899260	Issue Dt:	02/20/2018	Application #:	15002404	Filing Dt:	01/21/2016
Publication #:	US20170213764	Pub Dt:	07/27/2017
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

Patent #:	9748106	Issue Dt:	08/29/2017	Application #:	15002405	Filing Dt:	01/21/2016
Publication #:	US20170213740	Pub Dt:	07/27/2017
Title:	METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE

Patent #:	NONE	Issue Dt:		Application #:	15003765	Filing Dt:	01/21/2016
Publication #:	US20170213885	Pub Dt:	07/27/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF

Patent #:	NONE	Issue Dt:		Application #:	15003812	Filing Dt:	01/22/2016
Publication #:	US20170213801	Pub Dt:	07/27/2017
Title:	METHOD FOR MANUFACTURING A PACKAGE-ON-PACKAGE ASSEMBLY

Patent #:	9620675	Issue Dt:	04/11/2017	Application #:	15005794	Filing Dt:	01/25/2016
Publication #:	US20160225948	Pub Dt:	08/04/2016
Title:	SOLID STATE LIGHTING DEVICES WITH REDUCED CRYSTAL LATTICE DISLOCATIONS AND ASSOCIATED METHODS OF MANUFACTURING

Patent #:	9911608	Issue Dt:	03/06/2018	Application #:	15006134	Filing Dt:	01/26/2016
Publication #:	US20170213733	Pub Dt:	07/27/2017
Title:	METHOD OF FORMING PATTERNS

Patent #:	NONE	Issue Dt:		Application #:	15013995	Filing Dt:	02/02/2016
Publication #:	US20170219104	Pub Dt:	08/03/2017
Title:	THREE-WAY VALVE AND METHOD FOR USING THE SAME

Patent #:	9576931	Issue Dt:	02/21/2017	Application #:	15047632	Filing Dt:	02/19/2016
Title:	METHOD FOR FABRICATING WAFER LEVEL PACKAGE

Patent #:	9613895	Issue Dt:	04/04/2017	Application #:	15060577	Filing Dt:	03/03/2016
Title:	SEMICONDUCTOR PACKAGE WITH DOUBLE SIDE MOLDING

Patent #:	10073342	Issue Dt:	09/11/2018	Application #:	15060609	Filing Dt:	03/04/2016
Publication #:	US20170256417	Pub Dt:	09/07/2017
Title:	METHOD OF FORMING PATTERNS

Patent #:	9570369	Issue Dt:	02/14/2017	Application #:	15068649	Filing Dt:	03/14/2016
Title:	SEMICONDUCTOR PACKAGE WITH SIDEWALL-PROTECTED RDL INTERPOSER AND FABRICATION METHOD THEREOF

Patent #:	9704790	Issue Dt:	07/11/2017	Application #:	15069911	Filing Dt:	03/14/2016
Title:	METHOD OF FABRICATING A WAFER LEVEL PACKAGE

Patent #:	9613820	Issue Dt:	04/04/2017	Application #:	15069936	Filing Dt:	03/14/2016
Title:	METHOD OF FORMING PATTERNS

Patent #:	9990140	Issue Dt:	06/05/2018	Application #:	15077334	Filing Dt:	03/22/2016
Publication #:	US20160202913	Pub Dt:	07/14/2016
Title:	METHODS OF PROVIDING ACCESS TO I/O DEVICES

Patent #:	9721923	Issue Dt:	08/01/2017	Application #:	15098341	Filing Dt:	04/14/2016
Title:	SEMICONDUCTOR PACKAGE WITH MULTIPLE COPLANAR INTERPOSERS

Patent #:	9437583	Issue Dt:	09/06/2016	Application #:	15134396	Filing Dt:	04/21/2016
Title:	PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

Patent #:	9761559	Issue Dt:	09/12/2017	Application #:	15135539	Filing Dt:	04/21/2016
Title:	SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Patent #:	9585206	Issue Dt:	02/28/2017	Application #:	15137596	Filing Dt:	04/25/2016
Publication #:	US20160316528	Pub Dt:	10/27/2016
Title:	MULTI-JUNCTION SOLID STATE TRANSDUCER DEVICES FOR DIRECT AC POWER AND ASSOCIATED SYSTEMS AND METHODS

Patent #:	9881924	Issue Dt:	01/30/2018	Application #:	15151503	Filing Dt:	05/11/2016
Publication #:	US20170330882	Pub Dt:	11/16/2017
Title:	SEMICONDUCTOR MEMORY DEVICE HAVING COPLANAR DIGIT LINE CONTACTS AND STORAGE NODE CONTACTS IN MEMORY ARRAY AND METHOD FOR FABRICATING THE SAME

Patent #:	9786504	Issue Dt:	10/10/2017	Application #:	15155090	Filing Dt:	05/16/2016
Title:	METHOD FOR FORMING A PATTERNED LAYER

Patent #:	9735119	Issue Dt:	08/15/2017	Application #:	15219265	Filing Dt:	07/25/2016
Title:	CONDUCTIVE PADS FORMING METHOD

Patent #:	9786586	Issue Dt:	10/10/2017	Application #:	15242594	Filing Dt:	08/21/2016
Title:	SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Patent #:	9859285	Issue Dt:	01/02/2018	Application #:	15253894	Filing Dt:	09/01/2016
Publication #:	US20170213837	Pub Dt:	07/27/2017
Title:	METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING ENLARGED CELL CONTACT AREA

Patent #:	9985183	Issue Dt:	05/29/2018	Application #:	15262956	Filing Dt:	09/12/2016
Publication #:	US20160380156	Pub Dt:	12/29/2016
Title:	SOLID STATE LIGHTING DEVICES WITH ACCESSIBLE ELECTRODES AND METHODS OF MANUFACTURING

Patent #:	10833052	Issue Dt:	11/10/2020	Application #:	15286582	Filing Dt:	10/06/2016
Publication #:	US20180102311	Pub Dt:	04/12/2018
Title:	MICROELECTRONIC PACKAGE UTILIZING EMBEDDED BRIDGE THROUGH-SILICON-VIA INTERCONNECT COMPONENT AND RELATED METHODS

Patent #:	10872852	Issue Dt:	12/22/2020	Application #:	15291086	Filing Dt:	10/12/2016
Publication #:	US20180102313	Pub Dt:	04/12/2018
Title:	WAFER LEVEL PACKAGE UTILIZING MOLDED INTERPOSER

Patent #:	NONE	Issue Dt:		Application #:	15296053	Filing Dt:	10/18/2016
Publication #:	US20180107202	Pub Dt:	04/19/2018
Title:	SYSTEM AND METHOD FOR DETECTING FAULT EVENTS

Patent #:	9786514	Issue Dt:	10/10/2017	Application #:	15296058	Filing Dt:	10/18/2016
Publication #:	US20170263469	Pub Dt:	09/14/2017
Title:	SEMICONDUCTOR PACKAGE WITH SIDEWALL-PROTECTED RDL INTERPOSER

Patent #:	10483481	Issue Dt:	11/19/2019	Application #:	15298131	Filing Dt:	10/19/2016
Publication #:	US20170040563	Pub Dt:	02/09/2017
Title:	SOLID STATE OPTOELECTRONIC DEVICE WITH PLATED SUPPORT SUBSTRATE

Patent #:	10008395	Issue Dt:	06/26/2018	Application #:	15298156	Filing Dt:	10/19/2016
Publication #:	US20180108592	Pub Dt:	04/19/2018
Title:	STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL

Patent #:	10446195	Issue Dt:	10/15/2019	Application #:	15312010	Filing Dt:	11/17/2016
Publication #:	US20180226107	Pub Dt:	08/09/2018
Title:	VOLTAGE GENERATION CIRCUIT

Patent #:	9875786	Issue Dt:	01/23/2018	Application #:	15333507	Filing Dt:	10/25/2016
Publication #:	US20170040049	Pub Dt:	02/09/2017
Title:	OUTPUT BUFFER CIRCUIT WITH LOW SUB-THRESHOLD LEAKAGE CURRENT

Patent #:	10374156	Issue Dt:	08/06/2019	Application #:	15333774	Filing Dt:	10/25/2016
Publication #:	US20170040533	Pub Dt:	02/09/2017
Title:	MEMORY CELLS INCLUDING A METAL CHALCOGENIDE MATERIAL AND RELATED METHODS

Patent #:	9978730	Issue Dt:	05/22/2018	Application #:	15334069	Filing Dt:	10/25/2016
Publication #:	US20170040303	Pub Dt:	02/09/2017
Title:	METHOD OF ASSEMBLY SEMICONDUCTOR DEVICE WITH THROUGH-PACKAGE INTERCONNECT

Patent #:	10388871	Issue Dt:	08/20/2019	Application #:	15334186	Filing Dt:	10/25/2016
Publication #:	US20170040534	Pub Dt:	02/09/2017
Title:	Memory Cells and Methods of Forming Memory Cells

Patent #:	9666573	Issue Dt:	05/30/2017	Application #:	15335259	Filing Dt:	10/26/2016
Title:	Methods of Forming Integrated Circuitry

Patent #:	10048887	Issue Dt:	08/14/2018	Application #:	15336071	Filing Dt:	10/27/2016
Publication #:	US20180121128	Pub Dt:	05/03/2018
Title:	APPARATUSES AND METHODS FOR SINGLE LEVEL CELL CACHING

Patent #:	10157670	Issue Dt:	12/18/2018	Application #:	15338154	Filing Dt:	10/28/2016
Publication #:	US20180122468	Pub Dt:	05/03/2018
Title:	APPARATUSES INCLUDING MEMORY CELLS AND METHODS OF OPERATION OF SAME

Patent #:	10453704	Issue Dt:	10/22/2019	Application #:	15339290	Filing Dt:	10/31/2016
Publication #:	US20170047231	Pub Dt:	02/16/2017
Title:	METHOD FOR PACKAGING CIRCUITS

Patent #:	9997247	Issue Dt:	06/12/2018	Application #:	15339374	Filing Dt:	10/31/2016
Publication #:	US20170047120	Pub Dt:	02/16/2017
Title:	MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS

Patent #:	10424553	Issue Dt:	09/24/2019	Application #:	15339693	Filing Dt:	10/31/2016
Publication #:	US20180122762	Pub Dt:	05/03/2018
Title:	SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Patent #:	10290456	Issue Dt:	05/14/2019	Application #:	15339699	Filing Dt:	10/31/2016
Publication #:	US20170047187	Pub Dt:	02/16/2017
Title:	Methods of Forming and Using Fuses

Patent #:	10163917	Issue Dt:	12/25/2018	Application #:	15340682	Filing Dt:	11/01/2016
Publication #:	US20180122816	Pub Dt:	05/03/2018
Title:	CELL DISTURB PREVENTION USING A LEAKER DEVICE TO REDUCE EXCESS CHARGE FROM AN ELECTRONIC DEVICE

Patent #:	10014305	Issue Dt:	07/03/2018	Application #:	15340838	Filing Dt:	11/01/2016
Publication #:	US20180122817	Pub Dt:	05/03/2018
Title:	Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors

Patent #:	9761580	Issue Dt:	09/12/2017	Application #:	15340842	Filing Dt:	11/01/2016
Title:	METHODS OF FORMING AN ARRAY COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS AND ARRAYS COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS

Patent #:	10109351	Issue Dt:	10/23/2018	Application #:	15341410	Filing Dt:	11/02/2016
Publication #:	US20170053701	Pub Dt:	02/23/2017
Title:	PROGRAM AND READ TRIM SETTING

Patent #:	9922845	Issue Dt:	03/20/2018	Application #:	15342124	Filing Dt:	11/03/2016
Title:	SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Patent #:	9875802	Issue Dt:	01/23/2018	Application #:	15342255	Filing Dt:	11/03/2016
Publication #:	US20170076806	Pub Dt:	03/16/2017
Title:	ACCESS LINE MANAGEMENT IN A MEMORY DEVICE

Patent #:	10126967	Issue Dt:	11/13/2018	Application #:	15342287	Filing Dt:	11/03/2016
Publication #:	US20170075613	Pub Dt:	03/16/2017
Title:	SENSE OPERATION FLAGS IN A MEMORY DEVICE

Patent #:	10020252	Issue Dt:	07/10/2018	Application #:	15344211	Filing Dt:	11/04/2016
Publication #:	US20180130739	Pub Dt:	05/10/2018
Title:	WIRING WITH EXTERNAL TERMINAL

Patent #:	10163830	Issue Dt:	12/25/2018	Application #:	15344893	Filing Dt:	11/07/2016
Publication #:	US20170053881	Pub Dt:	02/23/2017
Title:	BONDING PADS WITH THERMAL PATHWAYS

Patent #:	9941466	Issue Dt:	04/10/2018	Application #:	15345636	Filing Dt:	11/08/2016
Publication #:	US20170077393	Pub Dt:	03/16/2017
Title:	MAGNETIC TUNNEL JUNCTIONS, METHODS USED WHILE FORMING MAGNETIC TUNNEL JUNCTIONS, AND METHODS OF FORMING MAGNETIC TUNNEL JUNCTIONS

Patent #:	10430085	Issue Dt:	10/01/2019	Application #:	15345783	Filing Dt:	11/08/2016
Publication #:	US20180129423	Pub Dt:	05/10/2018
Title:	MEMORY OPERATIONS ON DATA

Patent #:	10261876	Issue Dt:	04/16/2019	Application #:	15345862	Filing Dt:	11/08/2016
Publication #:	US20180129575	Pub Dt:	05/10/2018
Title:	MEMORY MANAGEMENT

Patent #:	10649665	Issue Dt:	05/12/2020	Application #:	15345919	Filing Dt:	11/08/2016
Publication #:	US20180129424	Pub Dt:	05/10/2018
Title:	DATA RELOCATION IN HYBRID MEMORY

100

Patent #:	10490257	Issue Dt:	11/26/2019	Application #:	15346526	Filing Dt:	11/08/2016
Publication #:	US20170053693	Pub Dt:	02/23/2017
Title:	COMPARISON OPERATIONS IN MEMORY

Assignor

MICRON TECHNOLOGY, INC.

Exec Dt:

01/24/2017

Assignee

MORGAN STANLEY SENIOR FUNDING, INC.

1300 THAMES STREET

4TH FLOOR

BALTIMORE, MARYLAND 21231

Correspondence name and address
	GENEVIEVE DORMENT, ESQ.
	SIMPSON THACHER & BARTLETT LLP
	425 LEXINGTON AVENUE
	NEW YORK, NY 10017

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