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Patent #:
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Issue Dt:
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11/27/2018
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Application #:
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15347271
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Filing Dt:
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11/09/2016
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Publication #:
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Pub Dt:
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03/02/2017
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Title:
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CLAMP ELEMENTS FOR PHASE CHANGE MEMORY ARRAYS
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Patent #:
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Issue Dt:
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12/12/2017
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Application #:
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15347623
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Filing Dt:
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11/09/2016
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Title:
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Transistors and Memory Arrays
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15348578
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Filing Dt:
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11/10/2016
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Title:
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APPARATUSES AND METHODS FOR POWER EFFICIENT DRIVER CIRCUITS
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Patent #:
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Issue Dt:
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09/24/2019
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Application #:
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15349492
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Filing Dt:
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11/11/2016
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Publication #:
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Pub Dt:
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05/17/2018
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Title:
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APPARATUSES AND METHODS FOR MEMORY ALIGNMENT
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Patent #:
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Issue Dt:
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05/15/2018
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Application #:
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15349808
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Filing Dt:
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11/11/2016
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Publication #:
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Pub Dt:
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05/17/2018
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Title:
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CONDUCTIVE STRUCTURES, WORDLINES AND TRANSISTORS
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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15350229
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Filing Dt:
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11/14/2016
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Publication #:
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Pub Dt:
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05/17/2018
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Title:
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METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENTIAL IN A MEMORY CELL
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15350926
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Filing Dt:
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11/14/2016
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Publication #:
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Pub Dt:
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03/02/2017
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Title:
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SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING INTERMETALLIC COMPOUND INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15351586
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Filing Dt:
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11/15/2016
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Publication #:
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Pub Dt:
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05/17/2018
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Title:
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TWO-STEP DATA-LINE PRECHARGE SCHEME
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Patent #:
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Issue Dt:
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09/11/2018
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Application #:
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15351977
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Filing Dt:
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11/15/2016
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Publication #:
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Pub Dt:
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03/02/2017
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Title:
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APPARATUS INCLUDING GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES
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Patent #:
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Issue Dt:
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01/29/2019
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Application #:
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15353473
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Filing Dt:
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11/16/2016
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Publication #:
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Pub Dt:
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03/02/2017
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Title:
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PROGRAMMABLE DEVICE, HEIRARCHICAL PARALLEL MACHINES, AND METHODS FOR PROVIDING STATE INFORMATION
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Patent #:
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Issue Dt:
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09/25/2018
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Application #:
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15354467
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Filing Dt:
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11/17/2016
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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SEMICONDUCTOR DEVICES AND PACKAGES AND METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15354572
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Filing Dt:
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11/17/2016
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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Methods of Forming Diodes
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Patent #:
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Issue Dt:
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12/11/2018
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Application #:
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15355621
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Filing Dt:
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11/18/2016
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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LINE TERMINATION METHODS
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Patent #:
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Issue Dt:
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12/18/2018
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Application #:
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15357593
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Filing Dt:
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11/21/2016
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR
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Patent #:
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Issue Dt:
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07/10/2018
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Application #:
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15357602
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Filing Dt:
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11/21/2016
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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Integrated Circuitry and Methods of Forming Transistors
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Patent #:
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Issue Dt:
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02/02/2021
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Application #:
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15357703
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Filing Dt:
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11/21/2016
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Publication #:
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Pub Dt:
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05/04/2017
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Title:
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METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A PATTERN RECOGNITION PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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09/12/2017
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Application #:
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15358673
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Filing Dt:
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11/22/2016
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Title:
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DATA SHIFT APPARATUSES AND METHODS
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15359218
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Filing Dt:
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11/22/2016
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Publication #:
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Pub Dt:
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03/16/2017
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Title:
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STAIR STEP FORMATION USING AT LEAST TWO MASKS
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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15359306
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Filing Dt:
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11/22/2016
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Publication #:
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Pub Dt:
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05/24/2018
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Title:
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BUFFER OPERATIONS IN MEMORY
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Patent #:
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Issue Dt:
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04/03/2018
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Application #:
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15361659
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Filing Dt:
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11/28/2016
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Publication #:
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Pub Dt:
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03/16/2017
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Title:
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SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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15362232
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Filing Dt:
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11/28/2016
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Publication #:
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Pub Dt:
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03/16/2017
| | | | |
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Title:
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BOOLEAN LOGIC IN A STATE MACHINE LATTICE
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Patent #:
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Issue Dt:
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04/03/2018
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Application #:
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15362435
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Filing Dt:
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11/28/2016
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Publication #:
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Pub Dt:
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03/16/2017
| | | | |
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Title:
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METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS AND SELECT GATES WITH DOUBLE GATES
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Patent #:
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Issue Dt:
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06/11/2019
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Application #:
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15364153
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Filing Dt:
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11/29/2016
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Publication #:
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Pub Dt:
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05/31/2018
| | | | |
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Title:
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MULTIFERROIC MAGNETIC TUNNEL JUNCTION DEVICES
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Patent #:
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Issue Dt:
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03/20/2018
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Application #:
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15365126
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Filing Dt:
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11/30/2016
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Title:
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Semiconductor Devices Comprising Nitrogen-Doped Gate Dielectric
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Patent #:
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Issue Dt:
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07/17/2018
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Application #:
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15365326
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Filing Dt:
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11/30/2016
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Publication #:
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Pub Dt:
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05/31/2018
| | | | |
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Title:
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WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF MIXING INPUT DATA WITH COEFFICIENT DATA
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Patent #:
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Issue Dt:
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04/10/2018
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Application #:
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15365397
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Filing Dt:
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11/30/2016
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Title:
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WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF MIXING COEFFICIENT DATA SPECIFIC TO A PROCESSING MODE SELECTION
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Patent #:
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Issue Dt:
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12/25/2018
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Application #:
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15365563
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Filing Dt:
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11/30/2016
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Publication #:
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Pub Dt:
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05/31/2018
| | | | |
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Title:
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SYSTEM AND METHOD FOR WRITE DATA BUS CONTROL IN A STACKED MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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15366198
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Filing Dt:
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12/01/2016
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Publication #:
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Pub Dt:
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06/15/2017
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Title:
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APPARATUSES AND METHODS FOR DYNAMIC VOLTAGE AND FREQUENCY SWITCHING FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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03/10/2020
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Application #:
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15366504
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Filing Dt:
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12/01/2016
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Publication #:
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Pub Dt:
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06/07/2018
| | | | |
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Title:
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MEMORY PROTOCOL
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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15367631
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Filing Dt:
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12/02/2016
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Publication #:
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Pub Dt:
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03/23/2017
| | | | |
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Title:
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APPARATUSES AND METHODS FOR PROVIDING DATA FROM A BUFFER
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Patent #:
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Issue Dt:
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08/28/2018
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Application #:
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15368158
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Filing Dt:
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12/02/2016
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Publication #:
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Pub Dt:
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03/23/2017
| | | | |
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Title:
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STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15369089
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Filing Dt:
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12/05/2016
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Publication #:
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Pub Dt:
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07/27/2017
| | | | |
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Title:
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SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT
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Patent #:
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Issue Dt:
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02/13/2018
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Application #:
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15369427
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Filing Dt:
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12/05/2016
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Publication #:
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Pub Dt:
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05/11/2017
| | | | |
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Title:
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METHODS OF FORMING RESISTIVE MEMORY ELEMENTS
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Patent #:
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|
Issue Dt:
|
10/02/2018
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Application #:
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15371044
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Filing Dt:
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12/06/2016
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Publication #:
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Pub Dt:
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03/23/2017
| | | | |
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Title:
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MEMORY MANAGEMENT FOR A HIERARCHICAL MEMORY SYSTEM
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Patent #:
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Issue Dt:
|
01/01/2019
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Application #:
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15372246
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Filing Dt:
|
12/07/2016
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Publication #:
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Pub Dt:
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06/07/2018
| | | | |
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Title:
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APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES
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|
|
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Patent #:
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|
Issue Dt:
|
09/24/2019
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Application #:
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15373158
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Filing Dt:
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12/08/2016
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Publication #:
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Pub Dt:
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06/14/2018
| | | | |
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Title:
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APPARATUS AND METHOD FOR A PVT INDEPENDENT RC DELAY
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Patent #:
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|
Issue Dt:
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06/25/2019
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Application #:
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15374831
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Filing Dt:
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12/09/2016
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Publication #:
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Pub Dt:
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06/14/2018
| | | | |
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Title:
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WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CROSS CORRELATING WIRELESS TRANSMISSIONS
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|
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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15375457
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Filing Dt:
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12/12/2016
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Publication #:
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Pub Dt:
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03/30/2017
| | | | |
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Title:
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METHODS OF FORMING CONDUCTIVE ELEMENTS OF SEMICONDUCTOR DEVICES AND OF FORMING MEMORY CELLS
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Patent #:
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|
Issue Dt:
|
09/04/2018
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Application #:
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15375507
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Filing Dt:
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12/12/2016
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Publication #:
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Pub Dt:
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03/30/2017
| | | | |
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Title:
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ARRAYS OF MEMORY CELLS AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS
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Patent #:
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|
Issue Dt:
|
10/18/2022
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Application #:
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15375976
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Filing Dt:
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12/12/2016
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Publication #:
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Pub Dt:
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03/30/2017
| | | | |
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Title:
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PHASE CHANGE MEMORY DEVICE WITH VOLTAGE CONTROL ELEMENTS
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Patent #:
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Issue Dt:
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01/02/2018
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Application #:
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15377767
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Filing Dt:
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12/13/2016
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Publication #:
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Pub Dt:
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09/14/2017
| | | | |
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Title:
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OFFSET COMPENSATION FOR FERROELECTRIC MEMORY CELL SENSING
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Patent #:
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Issue Dt:
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04/09/2019
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Application #:
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15378570
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Filing Dt:
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12/14/2016
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Publication #:
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Pub Dt:
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06/14/2018
| | | | |
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Title:
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BOARD EDGE CONNECTOR
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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15379933
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Filing Dt:
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12/15/2016
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Publication #:
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Pub Dt:
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04/06/2017
| | | | |
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Title:
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APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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15380877
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Filing Dt:
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12/15/2016
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Title:
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UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY
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Patent #:
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Issue Dt:
|
08/28/2018
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Application #:
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15381432
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Filing Dt:
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12/16/2016
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Publication #:
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Pub Dt:
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04/06/2017
| | | | |
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Title:
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ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
06/25/2019
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Application #:
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15382358
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Filing Dt:
|
12/16/2016
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|
Publication #:
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Pub Dt:
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04/13/2017
| | | | |
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Title:
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SEMICONDUCTOR DEVICE INCLUDING SUBWORD DRIVER CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
10/17/2017
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Application #:
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15382394
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Filing Dt:
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12/16/2016
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Publication #:
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Pub Dt:
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04/06/2017
| | | | |
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Title:
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SOFT POST PACKAGE REPAIR OF MEMORY DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
06/11/2019
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Application #:
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15383163
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Filing Dt:
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12/19/2016
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|
Publication #:
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Pub Dt:
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04/13/2017
| | | | |
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Title:
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SEQUENCE POWER CONTROL
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|
|
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Patent #:
|
|
Issue Dt:
|
03/01/2022
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Application #:
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15383260
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Filing Dt:
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12/19/2016
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|
Publication #:
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Pub Dt:
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04/06/2017
| | | | |
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Title:
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BLOCK OR PAGE LOCK FEATURES IN SERIAL INTERFACE MEMORY
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|
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Patent #:
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|
Issue Dt:
|
09/26/2017
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Application #:
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15385605
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Filing Dt:
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12/20/2016
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Publication #:
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|
Pub Dt:
|
04/13/2017
| | | | |
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Title:
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Transistors and Methods of Forming Transistors
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|
|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
15385690
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Filing Dt:
|
12/20/2016
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Publication #:
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Pub Dt:
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04/13/2017
| | | | |
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Title:
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LIGHT EMITTING DEVICES WITH BUILT-IN CHROMATICITY CONVERSION AND METHODS OF MANUFACTURING
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15385783
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Filing Dt:
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12/20/2016
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Publication #:
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Pub Dt:
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04/13/2017
| | | | |
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Title:
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Memory Arrays
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Patent #:
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Issue Dt:
|
08/28/2018
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Application #:
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15386343
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Filing Dt:
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12/21/2016
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Publication #:
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Pub Dt:
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06/21/2018
| | | | |
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Title:
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SEMICONDUCTOR DIE ASSEMBLY HAVING HEAT SPREADER THAT EXTENDS THROUGH UNDERLYING INTERPOSER AND RELATED TECHNOLOGY
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Patent #:
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Issue Dt:
|
06/06/2017
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Application #:
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15388971
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Filing Dt:
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12/22/2016
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Publication #:
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Pub Dt:
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04/13/2017
| | | | |
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Title:
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APPARATUSES AND METHODS FOR SETTING A SIGNAL IN VARIABLE RESISTANCE MEMORY
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Patent #:
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Issue Dt:
|
03/20/2018
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Application #:
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15390833
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Filing Dt:
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12/27/2016
|
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Title:
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IDENTIFYING ASYNCHRONOUS POWER LOSS
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|
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Patent #:
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Issue Dt:
|
06/26/2018
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Application #:
|
15390959
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Filing Dt:
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12/27/2016
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|
Publication #:
|
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Pub Dt:
|
06/28/2018
| | | | |
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Title:
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MEMORY DEVICES WHICH INCLUDE MEMORY ARRAYS
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|
|
|
Patent #:
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|
Issue Dt:
|
09/26/2017
|
Application #:
|
15391025
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Filing Dt:
|
12/27/2016
|
|
Title:
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Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
15391138
|
Filing Dt:
|
12/27/2016
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|
Publication #:
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|
Pub Dt:
|
06/28/2018
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Title:
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Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
15391405
|
Filing Dt:
|
12/27/2016
|
|
Title:
|
METHODS OF FORMING PATTERNS, AND APPARATUSES COMPRISING FINFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15391604
|
Filing Dt:
|
12/27/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
Methods of Forming Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
15391656
|
Filing Dt:
|
12/27/2016
|
|
Title:
|
Floating Body Transistors and Memory Arrays Comprising Floating Body Transistors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2017
|
Application #:
|
15391699
|
Filing Dt:
|
12/27/2016
|
|
Title:
|
Memory Arrays Comprising Ferroelectric Capacitors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15391719
|
Filing Dt:
|
12/27/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15392697
|
Filing Dt:
|
12/28/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
PHASE CHANGE MEMORY IN A DUAL INLINE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2017
|
Application #:
|
15393149
|
Filing Dt:
|
12/28/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
|
Title:
|
DEVICE HAVING MULTIPLE SWITCHING BUFFERS FOR DATA PATHS CONTROLLED BASED ON IO CONFIGURATION MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
15393553
|
Filing Dt:
|
12/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
|
Title:
|
CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15393719
|
Filing Dt:
|
12/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN 3D NON-VOLATILE MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2019
|
Application #:
|
15393919
|
Filing Dt:
|
12/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
|
Title:
|
PERSISTENT CONTENT IN NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
15395169
|
Filing Dt:
|
12/30/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
|
Title:
|
EXTERNAL GETTERING METHOD AND DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15395602
|
Filing Dt:
|
12/30/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/15/2017
| | | | |
|
Title:
|
CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15396259
|
Filing Dt:
|
12/30/2016
|
|
Title:
|
TIMING BASED ARBITER SYSTEMS AND CIRCUITS FOR ZQ CALIBRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15397919
|
Filing Dt:
|
01/04/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15398303
|
Filing Dt:
|
01/04/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15398475
|
Filing Dt:
|
01/04/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
15399315
|
Filing Dt:
|
01/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR STORING A DATA VALUE IN MULTIPLE COLUMNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15399372
|
Filing Dt:
|
01/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15399509
|
Filing Dt:
|
01/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2018
| | | | |
|
Title:
|
Magnetic Memory Device with Grid-Shaped Common Source Plate, System, and Method of Fabrication
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15399530
|
Filing Dt:
|
01/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS OF READING MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15399572
|
Filing Dt:
|
01/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND ERROR CORRECTION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2018
|
Application #:
|
15399664
|
Filing Dt:
|
01/05/2017
|
|
Title:
|
APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15399779
|
Filing Dt:
|
01/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2017
| | | | |
|
Title:
|
METHODS OF OPERATING STORAGE SYSTEMS INCLUDING ENCRYPTING A KEY SALT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
15400653
|
Filing Dt:
|
01/06/2017
|
|
Title:
|
APPARATUSES AND METHODS FOR A MEMORY DEVICE WITH DUAL COMMON DATA I/O LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2018
|
Application #:
|
15400886
|
Filing Dt:
|
01/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15401372
|
Filing Dt:
|
01/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
Methods Of Forming An Array Of Capacitors, Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor, Arrays Of Capacitors, And Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2020
|
Application #:
|
15401420
|
Filing Dt:
|
01/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
ERROR CORRECTION TO REDUCE A FAILURE IN TIME RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15401762
|
Filing Dt:
|
01/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGES WITH IMPROVED THERMAL MANAGEMENT AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2022
|
Application #:
|
15401888
|
Filing Dt:
|
01/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
EFFICIENT OPERATIONS OF COMPONENTS IN A WIRELESS COMMUNICATIONS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2018
|
Application #:
|
15401945
|
Filing Dt:
|
01/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
|
Title:
|
STACKED MEMORY DEVICES, SYSTEMS, AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2017
|
Application #:
|
15402463
|
Filing Dt:
|
01/10/2017
|
|
Title:
|
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15402679
|
Filing Dt:
|
01/10/2017
|
|
Title:
|
METHODS OF FORMING AN ARRAY COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS AND ARRAYS COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
15404407
|
Filing Dt:
|
01/12/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
DIRECTED SANITIZATION OF MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15404576
|
Filing Dt:
|
01/12/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
Memory Cells and Methods of Forming a Capacitor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2017
|
Application #:
|
15404995
|
Filing Dt:
|
01/12/2017
|
|
Title:
|
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
15405141
|
Filing Dt:
|
01/12/2017
|
|
Title:
|
Integrated Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2019
|
Application #:
|
15405711
|
Filing Dt:
|
01/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2018
| | | | |
|
Title:
|
INTERCONNECT STRUCTURE WITH NITRIDED BARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15405839
|
Filing Dt:
|
01/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2017
| | | | |
|
Title:
|
MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15407205
|
Filing Dt:
|
01/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2017
| | | | |
|
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2018
|
Application #:
|
15408272
|
Filing Dt:
|
01/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR HIGH SPEED WRITING TEST MODE FOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15409412
|
Filing Dt:
|
01/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2018
| | | | |
|
Title:
|
Memory Cells, Integrated Structures and Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
15410199
|
Filing Dt:
|
01/19/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2017
| | | | |
|
Title:
|
COMPARISON OPERATIONS IN MEMORY
|
|
