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Reel/Frame:030831/0119   Pages: 9
Recorded: 07/18/2013
Attorney Dkt #:92505-773017
Conveyance: ACQUISITION
Total properties: 23
1
Patent #:
7072825
Issue Dt:
07/04/2006
Application #:
10463057
Filing Dt:
06/16/2003
Publication #:
US20040254779
Pub Dt:
12/16/2004
Title:
HIERARCHICAL, NETWORK-BASED EMULATION SYSTEM
2
Patent #:
7117143
Issue Dt:
10/03/2006
Application #:
10735341
Filing Dt:
12/11/2003
Publication #:
US20050131670
Pub Dt:
06/16/2005
Title:
CLOCK DISTRIBUTION IN A CIRCUIT EMULATOR
3
Patent #:
7120571
Issue Dt:
10/10/2006
Application #:
10735342
Filing Dt:
12/11/2003
Publication #:
US20040254906
Pub Dt:
12/16/2004
Title:
RESOURCE BOARD FOR EMULATION SYSTEM
4
Patent #:
7366652
Issue Dt:
04/29/2008
Application #:
11230999
Filing Dt:
09/19/2005
Publication #:
US20060015313
Pub Dt:
01/19/2006
Title:
METHOD OF PROGRAMMING A CO-VERIFICATION SYSTEM
5
Patent #:
7703054
Issue Dt:
04/20/2010
Application #:
11697869
Filing Dt:
04/09/2007
Publication #:
US20080250378
Pub Dt:
10/09/2008
Title:
CIRCUIT EMULATION AND DEBUGGING METHOD
6
Patent #:
7895027
Issue Dt:
02/22/2011
Application #:
12015779
Filing Dt:
01/17/2008
Publication #:
US20090187394
Pub Dt:
07/23/2009
Title:
HDL RE-SIMULATION FROM CHECKPOINTS
7
Patent #:
7970597
Issue Dt:
06/28/2011
Application #:
12120895
Filing Dt:
05/15/2008
Publication #:
US20090287468
Pub Dt:
11/19/2009
Title:
EVENT-DRIVEN EMULATION SYSTEM
8
Patent #:
8255853
Issue Dt:
08/28/2012
Application #:
12756990
Filing Dt:
04/08/2010
Publication #:
US20110251836
Pub Dt:
10/13/2011
Title:
CIRCUIT EMULATION SYSTEMS AND METHODS
9
Patent #:
8336001
Issue Dt:
12/18/2012
Application #:
12913674
Filing Dt:
10/27/2010
Publication #:
US20110107278
Pub Dt:
05/05/2011
Title:
METHOD FOR IMPROVING YIELD RATE USING REDUNDANT WIRE INSERTION
10
Patent #:
8407647
Issue Dt:
03/26/2013
Application #:
12970888
Filing Dt:
12/16/2010
Publication #:
US20110154282
Pub Dt:
06/23/2011
Title:
SYSTEMS AND METHODS FOR DESIGNING AND MAKING INTEGRATED CIRCUITS WITH CONSIDERATION OF WIRING DEMAND RATIO
11
Patent #:
8281280
Issue Dt:
10/02/2012
Application #:
13025809
Filing Dt:
02/11/2011
Publication #:
US20110202894
Pub Dt:
08/18/2011
Title:
METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM
12
Patent #:
9081924
Issue Dt:
07/14/2015
Application #:
13047007
Filing Dt:
03/14/2011
Publication #:
US20110238397
Pub Dt:
09/29/2011
Title:
METHOD AND APPARATUS FOR TRANSACTION RECORDING AND VISUALIZATION
13
Patent #:
8522176
Issue Dt:
08/27/2013
Application #:
13103099
Filing Dt:
05/08/2011
Publication #:
US20110283247
Pub Dt:
11/17/2011
Title:
METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR THE TESTBENCH
14
Patent #:
8365132
Issue Dt:
01/29/2013
Application #:
13158471
Filing Dt:
06/13/2011
Publication #:
US20110320991
Pub Dt:
12/29/2011
Title:
HIERARCHIAL POWER MAP FOR LOW POWER DESIGN
15
Patent #:
8789008
Issue Dt:
07/22/2014
Application #:
13189014
Filing Dt:
07/22/2011
Publication #:
US20120066659
Pub Dt:
03/15/2012
Title:
METHODS FOR GENERATING DEVICE LAYOUTS BY COMBINING AN AUTOMATED DEVICE LAYOUT GENERATOR WITH A SCRIPT
16
Patent #:
9053264
Issue Dt:
06/09/2015
Application #:
13269085
Filing Dt:
10/07/2011
Publication #:
US20120239370
Pub Dt:
09/20/2012
Title:
WHAT-IF SIMULATION METHODS AND SYSTEMS
17
Patent #:
8683417
Issue Dt:
03/25/2014
Application #:
13289963
Filing Dt:
11/04/2011
Publication #:
US20120137264
Pub Dt:
05/31/2012
Title:
MULTIPLE LEVEL SPINE ROUTING
18
Patent #:
8959473
Issue Dt:
02/17/2015
Application #:
13289965
Filing Dt:
11/04/2011
Publication #:
US20120137265
Pub Dt:
05/31/2012
Title:
MULTIPLE LEVEL SPINE ROUTING
19
Patent #:
8671383
Issue Dt:
03/11/2014
Application #:
13443523
Filing Dt:
04/10/2012
Publication #:
US20130047134
Pub Dt:
02/21/2013
Title:
VIEWING AND DEBUGGING HDL DESIGNS HAVING SYSTEMVERILOG INTERFACE CONSTRUCTS
20
Patent #:
10152482
Issue Dt:
12/11/2018
Application #:
13449334
Filing Dt:
04/18/2012
Publication #:
US20130091098
Pub Dt:
04/11/2013
Title:
METHOD OF SPEEDING UP ACCESS TO DESIGN DATABASES HAVING LARGE NUMBERS OF DESIGN UNITS
21
Patent #:
8732650
Issue Dt:
05/20/2014
Application #:
13597997
Filing Dt:
08/29/2012
Publication #:
US20130035925
Pub Dt:
02/07/2013
Title:
METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM
22
Patent #:
8832632
Issue Dt:
09/09/2014
Application #:
13660887
Filing Dt:
10/25/2012
Title:
COMPACT ROUTING
23
Patent #:
8875081
Issue Dt:
10/28/2014
Application #:
13778071
Filing Dt:
02/26/2013
Publication #:
US20140068542
Pub Dt:
03/06/2014
Title:
Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio
Assignor
1
SPRINGSOFT, INC.
Exec Dt:
12/03/2012
Assignee
1
SYNOPSYS TAIWAN CO., LTD.
4F-1, #28, TAI-YUAN STREET
CHUPEI CITY, HSINCHU HSIEN, TAIWAN 302
Correspondence name and address
KILPATRICK TOWNSEND & STOCKTON LLP
TWO EMBARCADERO CENTER, 8TH FLOOR
SAN FRANCISCO, CA 94111-3834

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