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414
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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11964015
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Filing Dt:
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12/25/2007
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
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VOLTAGE REGULATOR INTEGRATED WITH SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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11981125
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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04/17/2008
| | | | |
Title:
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STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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11981138
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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03/20/2008
| | | | |
Title:
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A STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12001676
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Filing Dt:
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12/12/2007
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Publication #:
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Pub Dt:
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05/29/2008
| | | | |
Title:
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TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/13/2011
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Application #:
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12014812
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Filing Dt:
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01/16/2008
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Publication #:
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Pub Dt:
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06/05/2008
| | | | |
Title:
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POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
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Patent #:
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Issue Dt:
|
04/19/2011
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Application #:
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12019635
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Filing Dt:
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01/25/2008
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Publication #:
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Pub Dt:
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05/22/2008
| | | | |
Title:
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POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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12019644
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Filing Dt:
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01/25/2008
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Publication #:
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Pub Dt:
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06/12/2008
| | | | |
Title:
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POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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12024998
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Filing Dt:
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02/02/2008
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Publication #:
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Pub Dt:
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06/19/2008
| | | | |
Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12024999
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Filing Dt:
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02/02/2008
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Publication #:
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Pub Dt:
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05/29/2008
| | | | |
Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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01/27/2009
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Application #:
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12025000
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Filing Dt:
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02/02/2008
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Publication #:
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Pub Dt:
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06/19/2008
| | | | |
Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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12025001
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Filing Dt:
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02/02/2008
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Publication #:
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Pub Dt:
|
05/29/2008
| | | | |
Title:
|
CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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|
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Patent #:
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|
Issue Dt:
|
12/09/2008
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Application #:
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12025002
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Filing Dt:
|
02/02/2008
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Publication #:
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Pub Dt:
|
06/19/2008
| | | | |
Title:
|
METHOD FOR FABRICATING A CIRCUIT COMPONENT
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Patent #:
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Issue Dt:
|
03/29/2011
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Application #:
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12032706
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Filing Dt:
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02/18/2008
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Publication #:
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Pub Dt:
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06/19/2008
| | | | |
Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
|
03/15/2011
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Application #:
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12032707
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Filing Dt:
|
02/18/2008
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Publication #:
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Pub Dt:
|
06/12/2008
| | | | |
Title:
|
CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
|
01/31/2012
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Application #:
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12034668
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Filing Dt:
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02/21/2008
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Publication #:
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Pub Dt:
|
06/19/2008
| | | | |
Title:
|
SOFTWARE PROGRAMMABLE MULTIPLE FUNCTION INTEGRATED CIRCUIT MODULE
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12036306
|
Filing Dt:
|
02/25/2008
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
Top layers of metal for high performance IC's
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|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12036308
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Filing Dt:
|
02/25/2008
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12036309
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Filing Dt:
|
02/25/2008
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
Top layers of metal for high performance IC's
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|
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Patent #:
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|
Issue Dt:
|
06/05/2012
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Application #:
|
12045029
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Filing Dt:
|
03/10/2008
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Publication #:
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Pub Dt:
|
11/20/2008
| | | | |
Title:
|
CHIP ASSEMBLY WITH INTERCONNECTION BY METAL BUMP
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|
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Patent #:
|
|
Issue Dt:
|
09/06/2011
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Application #:
|
12098465
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Filing Dt:
|
04/07/2008
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Publication #:
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|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE
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|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
12098467
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Filing Dt:
|
04/07/2008
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Title:
|
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12098468
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Filing Dt:
|
04/07/2008
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Publication #:
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|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
Low fabrication cost, fine pitch and high reliability solder bump
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12098469
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Filing Dt:
|
04/07/2008
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Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
Low fabrication cost, fine pitch and high reliability solder bump
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|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12101127
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
CHIP PACKAGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12109367
|
Filing Dt:
|
04/25/2008
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
Method of assembling chips
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12121778
|
Filing Dt:
|
05/15/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
Method of assembling chips
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12127794
|
Filing Dt:
|
05/27/2008
|
Publication #:
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|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
CHIP STRUCTURE WITH BUMPS AND TESTING PADS
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|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12128644
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Filing Dt:
|
05/29/2008
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Publication #:
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|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
METHOD OF JOINING CHIPS UTILIZING COPPER PILLAR
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|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12132626
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Filing Dt:
|
06/04/2008
|
Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
12132628
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Filing Dt:
|
06/04/2008
|
Publication #:
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|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
CYLINDRICAL BONDING STRUCTURE AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12138453
|
Filing Dt:
|
06/13/2008
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
Title:
|
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12138455
|
Filing Dt:
|
06/13/2008
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12142825
|
Filing Dt:
|
06/20/2008
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12142829
|
Filing Dt:
|
06/20/2008
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12172275
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
12182145
|
Filing Dt:
|
07/30/2008
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12182148
|
Filing Dt:
|
07/30/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12186523
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
Title:
|
Top layers of metal for high performance IC's
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12186530
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12198899
|
Filing Dt:
|
08/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/20/2009
| | | | |
Title:
|
WIREBOND OVER POST PASSIVATION THICK METAL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12202341
|
Filing Dt:
|
09/01/2008
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
CHIP PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12202342
|
Filing Dt:
|
09/01/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
CHIP STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12203154
|
Filing Dt:
|
09/03/2008
|
Publication #:
|
|
Pub Dt:
|
02/19/2009
| | | | |
Title:
|
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
12206751
|
Filing Dt:
|
09/09/2008
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
CHIP PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
12206754
|
Filing Dt:
|
09/09/2008
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
METHOD OF FABRICATING CHIP PACKAGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12208353
|
Filing Dt:
|
09/11/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
High performance system-on-chip using post passivation process
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12260086
|
Filing Dt:
|
10/28/2008
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
Title:
|
METHOD OF MANUFACTURE AND IDENTIFICATION OF SEMICONDUCTOR CHIP MARKED FOR IDENTIFICATION WITH INTERNAL MARKING INDICIA AND PROTECTION THEREOF BY NON-BLACK LAYER AND DEVICE PRODUCED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
12262195
|
Filing Dt:
|
10/31/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
STRUCTURE OF GOLD BUMPS AND GOLD CONDUCTORS ON ONE IC DIE AND METHODS OF MANUFACTURING THE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12264271
|
Filing Dt:
|
11/04/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
POST PASSIVATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND PACKAGING PROCESS FOR SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12269045
|
Filing Dt:
|
11/12/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12269053
|
Filing Dt:
|
11/12/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12269054
|
Filing Dt:
|
11/12/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
Multiple chips bonded to packaging structure with low noise and multiple selectable functions
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12269064
|
Filing Dt:
|
11/12/2008
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12269065
|
Filing Dt:
|
11/12/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12273546
|
Filing Dt:
|
11/19/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
OVER-PASSIVATION PROCESS OF FORMING POLYMER LAYER OVER IC CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12273548
|
Filing Dt:
|
11/19/2008
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
SEMICONDUCTOR CHIP AND PROCESS FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12276419
|
Filing Dt:
|
11/24/2008
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12353250
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
CHIP PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12353251
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12353252
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12353254
|
Filing Dt:
|
01/13/2009
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Publication #:
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Pub Dt:
|
05/14/2009
| | | | |
Title:
|
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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Patent #:
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|
Issue Dt:
|
01/11/2011
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Application #:
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12353255
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Filing Dt:
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01/13/2009
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Publication #:
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Pub Dt:
|
05/14/2009
| | | | |
Title:
|
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
12365180
|
Filing Dt:
|
02/04/2009
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Publication #:
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Pub Dt:
|
07/23/2009
| | | | |
Title:
|
System-on-chip with post passivation capacitor
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Patent #:
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|
Issue Dt:
|
02/01/2011
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Application #:
|
12370617
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Filing Dt:
|
02/13/2009
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Publication #:
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Pub Dt:
|
06/11/2009
| | | | |
Title:
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POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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Patent #:
|
NONE
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Issue Dt:
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Application #:
|
12384977
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Filing Dt:
|
04/09/2009
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Publication #:
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Pub Dt:
|
10/29/2009
| | | | |
Title:
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Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
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Patent #:
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|
Issue Dt:
|
08/14/2012
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Application #:
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12464896
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Filing Dt:
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05/13/2009
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Publication #:
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Pub Dt:
|
09/03/2009
| | | | |
Title:
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SEMICONDUCTOR CHIP WITH PASSIVATION LAYER COMPRISING METAL INTERCONNECT AND CONTACT PADS
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Patent #:
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Issue Dt:
|
12/06/2011
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Application #:
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12493258
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Filing Dt:
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06/29/2009
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Publication #:
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Pub Dt:
|
10/22/2009
| | | | |
Title:
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LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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Patent #:
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|
Issue Dt:
|
07/12/2016
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Application #:
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12506278
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Filing Dt:
|
07/21/2009
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Publication #:
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Pub Dt:
|
01/21/2010
| | | | |
Title:
|
CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
04/23/2013
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Application #:
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12512073
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Filing Dt:
|
07/30/2009
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Publication #:
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|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
Structure and manufacturing method of chip scale package
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|
Patent #:
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|
Issue Dt:
|
05/01/2012
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Application #:
|
12534885
|
Filing Dt:
|
08/04/2009
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Publication #:
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|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME
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|
|
Patent #:
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|
Issue Dt:
|
11/11/2014
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Application #:
|
12545880
|
Filing Dt:
|
08/24/2009
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Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
Title:
|
CIRCUITRY COMPONENT AND METHOD FOR FORMING THE SAME
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
12645361
|
Filing Dt:
|
12/22/2009
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Publication #:
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|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
CHIP PACKAGES WITH POWER MANAGEMENT INTEGRATED CIRCUITS AND RELATED TECHNIQUES
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Patent #:
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Issue Dt:
|
01/08/2013
|
Application #:
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12691597
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Filing Dt:
|
01/21/2010
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Publication #:
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|
Pub Dt:
|
05/13/2010
| | | | |
Title:
|
TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S
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|
Patent #:
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|
Issue Dt:
|
06/05/2012
|
Application #:
|
12703139
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Filing Dt:
|
02/09/2010
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Publication #:
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|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
IMAGE AND LIGHT SENSOR CHIP PACKAGES
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
|
Application #:
|
12722483
|
Filing Dt:
|
03/11/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY
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|
Patent #:
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|
Issue Dt:
|
04/17/2012
|
Application #:
|
12748295
|
Filing Dt:
|
03/26/2010
|
Publication #:
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|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
CHIP PACKAGES
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|
Patent #:
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|
Issue Dt:
|
04/24/2012
|
Application #:
|
12779863
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
SYSTEM-IN PACKAGES
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|
|
Patent #:
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|
Issue Dt:
|
08/06/2013
|
Application #:
|
12841981
|
Filing Dt:
|
07/22/2010
|
Publication #:
|
|
Pub Dt:
|
02/03/2011
| | | | |
Title:
|
SYSTEM-IN PACKAGES
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12852467
|
Filing Dt:
|
08/07/2010
|
Publication #:
|
|
Pub Dt:
|
02/03/2011
| | | | |
Title:
|
STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
12852470
|
Filing Dt:
|
08/07/2010
|
Publication #:
|
|
Pub Dt:
|
02/03/2011
| | | | |
Title:
|
STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12941069
|
Filing Dt:
|
11/07/2010
|
Publication #:
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|
Pub Dt:
|
03/03/2011
| | | | |
Title:
|
CHIP STRUCTURE WITH BUMPS AND TESTING PADS
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|
|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
|
13031163
|
Filing Dt:
|
02/18/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
|
Application #:
|
13071203
|
Filing Dt:
|
03/24/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
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|
Patent #:
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|
Issue Dt:
|
02/26/2013
|
Application #:
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13077009
|
Filing Dt:
|
03/31/2011
|
Publication #:
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Pub Dt:
|
07/21/2011
| | | | |
Title:
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METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13094780
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Filing Dt:
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04/26/2011
|
Publication #:
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|
Pub Dt:
|
08/18/2011
| | | | |
Title:
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SEMICONDUCTOR CHIP WITH A BONDING PAD HAVING CONTACT AND TEST AREAS
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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13098340
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Filing Dt:
|
04/29/2011
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Publication #:
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Pub Dt:
|
08/25/2011
| | | | |
Title:
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CIRCUIT COMPONENT WITH CONDUCTIVE LAYER STRUCTURE
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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13098379
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Filing Dt:
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04/29/2011
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Publication #:
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|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
CHIP STRUCTURE
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13105866
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Filing Dt:
|
05/11/2011
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Publication #:
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Pub Dt:
|
09/01/2011
| | | | |
Title:
|
CHIP PACKAGE
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Patent #:
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Issue Dt:
|
05/07/2013
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Application #:
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13107058
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Filing Dt:
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05/13/2011
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Publication #:
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Pub Dt:
|
09/08/2011
| | | | |
Title:
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CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
06/11/2013
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Application #:
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13108743
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Filing Dt:
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05/16/2011
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Publication #:
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Pub Dt:
|
09/08/2011
| | | | |
Title:
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METHOD FOR FABRICATING CIRCUIT COMPONENT
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13108811
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Filing Dt:
|
05/16/2011
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Publication #:
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Pub Dt:
|
09/08/2011
| | | | |
Title:
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DOUBLE EMBOSSING STRUCTURE
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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13159147
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
|
09/29/2011
| | | | |
Title:
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SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER
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Patent #:
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Issue Dt:
|
07/23/2013
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Application #:
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13159190
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
|
12/22/2011
| | | | |
Title:
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SEMICONDUCTOR PACKAGE WITH INTERCONNECT LAYERS
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Patent #:
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Issue Dt:
|
04/23/2013
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Application #:
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13159368
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
|
10/06/2011
| | | | |
Title:
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STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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13174317
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Filing Dt:
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06/30/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
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Patent #:
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Issue Dt:
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04/08/2014
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Application #:
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13180479
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Filing Dt:
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07/11/2011
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Publication #:
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Pub Dt:
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11/03/2011
| | | | |
Title:
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CARBON NANOTUBE CIRCUIT COMPONENT STRUCTURE
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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13181255
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Filing Dt:
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07/12/2011
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Publication #:
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Pub Dt:
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11/03/2011
| | | | |
Title:
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SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER
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Patent #:
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Issue Dt:
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10/01/2013
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Application #:
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13191356
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Filing Dt:
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07/26/2011
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Publication #:
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Pub Dt:
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11/17/2011
| | | | |
Title:
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CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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13197630
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Filing Dt:
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08/03/2011
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Publication #:
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Pub Dt:
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11/24/2011
| | | | |
Title:
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INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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13197633
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Filing Dt:
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08/03/2011
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Publication #:
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Pub Dt:
|
11/24/2011
| | | | |
Title:
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MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE
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