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Patent Assignment Details
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Reel/Frame:033303/0124   Pages: 80
Recorded: 07/11/2014
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 414
Page 5 of 5
Pages: 1 2 3 4 5
1
Patent #:
Issue Dt:
08/27/2013
Application #:
13207346
Filing Dt:
08/10/2011
Publication #:
Pub Dt:
12/01/2011
Title:
CHIP STRUCTURE
2
Patent #:
Issue Dt:
04/16/2013
Application #:
13207350
Filing Dt:
08/10/2011
Publication #:
Pub Dt:
12/01/2011
Title:
A CHIP PACKAGE HAVING A CHIP COMBINED WITH A SUBSTRATE VIA A COPPER PILLAR
3
Patent #:
Issue Dt:
02/05/2013
Application #:
13236507
Filing Dt:
09/19/2011
Publication #:
Pub Dt:
01/12/2012
Title:
CHIP PACKAGE
4
Patent #:
Issue Dt:
06/03/2014
Application #:
13271004
Filing Dt:
10/11/2011
Publication #:
Pub Dt:
02/02/2012
Title:
SOLDER INTERCONNECT ON IC CHIP
5
Patent #:
Issue Dt:
02/05/2013
Application #:
13277142
Filing Dt:
10/19/2011
Publication #:
Pub Dt:
04/26/2012
Title:
CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
6
Patent #:
Issue Dt:
10/07/2014
Application #:
13475820
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
09/13/2012
Title:
IMAGE AND LIGHT SENSOR CHIP PACKAGES
7
Patent #:
NONE
Issue Dt:
Application #:
13735894
Filing Dt:
01/07/2013
Publication #:
Pub Dt:
01/23/2014
Title:
HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE
8
Patent #:
Issue Dt:
12/31/2013
Application #:
13735987
Filing Dt:
01/07/2013
Publication #:
Pub Dt:
05/23/2013
Title:
INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL
9
Patent #:
NONE
Issue Dt:
Application #:
13851050
Filing Dt:
03/26/2013
Publication #:
Pub Dt:
08/22/2013
Title:
Methods for Fabricating an Integrated Circuit Having a Post-Passivation Thin-Film Resistor
10
Patent #:
Issue Dt:
12/16/2014
Application #:
13853878
Filing Dt:
03/29/2013
Publication #:
Pub Dt:
08/29/2013
Title:
STRUCTURE AND MANUFACTURING METHOD OF CHIP SCALE PACKAGE
11
Patent #:
Issue Dt:
04/04/2017
Application #:
13874983
Filing Dt:
05/01/2013
Publication #:
Pub Dt:
09/19/2013
Title:
INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY
12
Patent #:
Issue Dt:
09/16/2014
Application #:
13887093
Filing Dt:
05/03/2013
Publication #:
Pub Dt:
11/21/2013
Title:
INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
13
Patent #:
Issue Dt:
08/12/2014
Application #:
13935135
Filing Dt:
07/03/2013
Publication #:
Pub Dt:
11/07/2013
Title:
SYSTEM-IN PACKAGES
14
Patent #:
Issue Dt:
08/19/2014
Application #:
14034440
Filing Dt:
09/23/2013
Publication #:
Pub Dt:
01/23/2014
Title:
CHIP PACKAGES HAVING DUAL DMOS DEVICES WITH POWER MANAGEMENT INTEGRATED CIRCUITS
Assignor
1
Exec Dt:
07/09/2014
Assignee
1
5775 MOREHOUSE DRIVE
SAN DIEGO, CALIFORNIA 92121
Correspondence name and address
QUALCOMM INCORPORATED
5775 MOREHOUSE DRIVE
SAN DIEGO, CA 92121

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