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Total properties:
16
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08486690
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Filing Dt:
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06/07/1995
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Title:
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ANALOG-TO-DIGITAL CONVERTER WITH LOCAL FEEDBACK
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08558636
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Filing Dt:
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11/13/1995
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Title:
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PIPELINED DIGITAL SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM EMPLOYING SAME
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08580272
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Filing Dt:
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12/27/1995
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Title:
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MERGED MULTI-STAGE COMB FILTER WITH REDUCED OPERATIONAL REQUIREMENTS
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Patent #:
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Issue Dt:
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02/24/1998
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Application #:
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08582644
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Filing Dt:
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01/04/1996
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Title:
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ANALOG-TO-DIGITAL CONVERTER EMPLOYING DC OFFSET CANCELLATION AFTER MODULATION AND BEFORE DIGITAL PROCESSING
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08630390
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Filing Dt:
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04/10/1996
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Title:
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AN APPARATUS AND METHOD FOR SWITCHING CAPACITORS WITHIN A SWITCHED CAPACITOR CIRCUIT AT TIMES SELECTED TO AVOID DATA DEPENDENT LOADING UPON REFERENCE VOLTAGE SUPPLIES
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Patent #:
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Issue Dt:
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03/17/1998
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Application #:
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08630436
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Filing Dt:
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04/10/1996
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Title:
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COMBINATION SHARED CAPACITOR INTEGRATOR AND DIGITAL-TO-ANALOG CONVERTER CIRCUIT WITH DATA DEPENDENCY CANCELLATION
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08951650
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Filing Dt:
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10/16/1997
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Title:
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A PHASE-LOCKED LOOP WHICH CAN AUTOMATICALLY ADJUST TO AND LOCK UPON A VARIABLE INPUT FREQUENCY
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08951796
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Filing Dt:
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10/16/1997
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Title:
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PHASE-LOCKED LOOP WITH PROTECTED OUTPUT DURING INSTANCES WHEN THE PHASE-LOCKED LOOP IS UNLOCKED
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09025157
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Filing Dt:
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02/18/1998
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Title:
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APPARATUS AND METHOD FOR CLOCKING DIGITAL AND ANALOG CIRCUITS ON A COMMON SUBSTRATE TO ENHANCE DIGITAL OPERATION AND REDUCE ANALOG SAMPLING ERROR
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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09253469
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Filing Dt:
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02/19/1999
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Title:
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COMMUNICATION SYSTEM EMPLOYING A NETWORK OF POWER MANAGED TRANSCEIVERS THAT CAN GENERATE A CLOCKING SIGNAL OR ENABLE DATA BYPASS OF A DIGITAL SYSTEM ASSOCIATED WITH EACH TRANSCEIVER
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09710220
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Filing Dt:
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11/10/2000
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Title:
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ENCODER WITHIN A COMMUNICATION SYSTEM THAT AVOIDS ENCODED DC ACCUMULATION AND CAN USE CODING VIOLATIONS TO SYNCHRONIZE A DECODER AND DETECT TRANSMISSION ERRORS
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10157097
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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COMMUNICATION SYSTEM AND METHODOLOGY FOR ADDRESSING AND SENDING DATA OF DISSIMILAR TYPE AND SIZE ACROSS CHANNELS FORMED WITHIN A LOCALLY SYNCHRONIZED BUS
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10157673
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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COMMUNICATION SYSTEM AND METHODOLOGY FOR SENDING A DESIGNATOR FOR AT LEAST ONE OF A SET OF TIME-DIVISION MULTIPLEXED CHANNELS FORWARDED ACROSS A LOCALLY SYNCHRONIZED BUS
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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10180696
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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COMMUNICATION SYSTEM AND METHOD FOR SENDING ISOCHRONOUS STREAMING DATA WITHIN A FRAME SEGMENT USING A SIGNALING BYTE
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10180729
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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COMMUNICATION SYSTEM AND METHOD FOR SENDING ASYNCHRONOUS DATA AND/OR ISOCHRONOUS STREAMING DATA ACROSS A SYNCHRONOUS NETWORK WITHIN A FRAME SEGMENT USING A CODING VIOLATION TO SIGNIFY AT LEAST THE BEGINNING OF A DATA TRANSFER
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Patent #:
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Issue Dt:
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01/16/2007
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Application #:
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10180741
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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COMMUNICATION SYSTEM AND METHOD FOR SENDING ISOCHRONOUS STREAMING DATA ACROSS A SYNCHRONOUS NETWORK WITHIN A FRAME SEGMENT USING A CODING VIOLATION TO SIGNIFY INVALID OR EMPTY BYTES WITHIN THE FRAME SEGMENT
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