Patent Assignment Details
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Reel/Frame: | 010716/0136 | |
| Pages: | 2 |
| | Recorded: | 04/06/2000 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09461298
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Filing Dt:
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12/15/1999
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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LOGIC CONSOLIDATED SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CIRCUIT AND LOGIC CIRCUIT INTEGRATED IN THE SAME CHIP
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Assignee
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SARUGAKUCHO 2-8-8, CHIYODA-KU |
TOKYO, JAPAN |
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Correspondence name and address
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TOWNSEND & BANTA
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DONALD E. TOWNSEND, JR.
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1225 EYE STREET N.W., SUITE 500
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WASHINGTON, DC 20005
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