Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 033477/0142 | |
| Pages: | 2 |
| | Recorded: | 08/06/2014 | | |
Attorney Dkt #: | 14457 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2015
|
Application #:
|
14453015
|
Filing Dt:
|
08/06/2014
|
Publication #:
|
|
Pub Dt:
|
02/12/2015
| | | | |
Title:
|
High-Frequency MOS Transistor Layout to Reduce Parasitic Gate Resistance and Parasitic Gate-to-Drain Capacitance
|
|
Assignee
|
|
|
1-1, SHIBAURA 1-CHOME |
MINATO-KU, TOKYO, JAPAN 105-8001 |
|
Correspondence name and address
|
|
HOLTZ, HOLTZ, GOODMAN & CHICK PC
|
|
220 FIFTH AVENUE
|
|
16TH FLOOR
|
|
NEW YORK, NY 10001-7708
|
Search Results as of:
09/23/2024 07:07 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|