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Total properties:
20
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|
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Patent #:
|
|
Issue Dt:
|
06/21/2016
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Application #:
|
14093703
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Filing Dt:
|
12/02/2013
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|
Publication #:
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|
Pub Dt:
|
06/04/2015
| | | | |
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Title:
|
GENERATION OF WAKE-UP WORDS
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|
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14095150
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Filing Dt:
|
12/03/2013
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|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
|
Title:
|
Reduction of Charging Induced Damage in Photolithography Wet Process
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/19/2015
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Application #:
|
14099340
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Filing Dt:
|
12/06/2013
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|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
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Title:
|
METHOD AND APPARATUS FOR STAGGERED START-UP OF A PREDEFINED, RANDOM OR DYNAMIC NUMBER OF FLASH MEMORY DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
01/26/2016
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Application #:
|
14107729
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Filing Dt:
|
12/16/2013
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|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
|
Title:
|
Output Voltage Controller, Electronic Device, and Output Voltage Control Method
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/11/2016
|
Application #:
|
14108780
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Filing Dt:
|
12/17/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2015
| | | | |
|
Title:
|
PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
14109157
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Filing Dt:
|
12/17/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
|
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2016
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Application #:
|
14132422
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Filing Dt:
|
12/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2015
| | | | |
|
Title:
|
INCREASING LITHOGRAPHIC DEPTH OF FOCUS WINDOW USING WAFER TOPOGRAPHY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14135863
|
Filing Dt:
|
12/20/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
|
Title:
|
CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
14136358
|
Filing Dt:
|
12/20/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
|
Title:
|
GATE FORMATION MEMORY BY PLANARIZATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14143317
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Filing Dt:
|
12/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
|
Title:
|
Formation of Gate Sidewall Structure
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14149484
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Filing Dt:
|
01/07/2014
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
|
Title:
|
DATA WRITING METHOD AND SYSTEM
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14149628
|
Filing Dt:
|
01/07/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
|
Title:
|
MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14169549
|
Filing Dt:
|
01/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
14180444
|
Filing Dt:
|
02/14/2014
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
|
Title:
|
AUTHENTICATED MEMORY AND CONTROLLER SLAVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
|
Application #:
|
14188048
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Filing Dt:
|
02/24/2014
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
|
Title:
|
MEMORY SUBSYSTEM WITH WRAPPED-TO-CONTINUOUS READ
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14199837
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Filing Dt:
|
03/06/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
|
Title:
|
Memory Access Bases on Erase Cycle Time
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14204373
|
Filing Dt:
|
03/11/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14207303
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Filing Dt:
|
03/12/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
|
Title:
|
BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2016
|
Application #:
|
14220628
|
Filing Dt:
|
03/20/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
CONTROL CIRCUIT OF STEP-DOWN DC-DC CONVERTER, CONTROL CIRCUIT OF STEP-UP DC-DC CONVERTER AND STEP-UP/STEP-DOWN DC-DC CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
14228384
|
Filing Dt:
|
03/28/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
|
|
