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Patent Assignment Details
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Reel/Frame:036032/0154   Pages: 152
Recorded: 06/29/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
6329257
Issue Dt:
12/11/2001
Application #:
08994140
Filing Dt:
12/19/1997
Title:
METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
2
Patent #:
6321280
Issue Dt:
11/20/2001
Application #:
09241082
Filing Dt:
02/01/1999
Title:
SYSTEM LSI HAVING COMMUNICATION FUNCTION
3
Patent #:
6309927
Issue Dt:
10/30/2001
Application #:
09263983
Filing Dt:
03/05/1999
Publication #:
US20010046738
Pub Dt:
11/29/2001
Title:
METHOD OF FORMING HIGH K TANTALUM PENTOXIDE TA205 INSTEAD OF ONO STACKED FILMS TO INCREASE COUPLING RATIO AND IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
4
Patent #:
6323047
Issue Dt:
11/27/2001
Application #:
09368247
Filing Dt:
08/03/1999
Title:
METHOD FOR MONITORING SECOND GATE OVER-ETCH IN A SEMICONDUCTOR DEVICE
5
Patent #:
6323516
Issue Dt:
11/27/2001
Application #:
09390052
Filing Dt:
09/03/1999
Title:
FLASH MEMORY DEVICE AND FABRICATION METHOD HAVING A HIGH COUPLING RATIO
6
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
7
Patent #:
6326268
Issue Dt:
12/04/2001
Application #:
09426427
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
8
Patent #:
6329273
Issue Dt:
12/11/2001
Application #:
09430410
Filing Dt:
10/29/1999
Title:
SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
9
Patent #:
6319775
Issue Dt:
11/20/2001
Application #:
09433037
Filing Dt:
10/25/1999
Title:
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
10
Patent #:
6309949
Issue Dt:
10/30/2001
Application #:
09440934
Filing Dt:
11/16/1999
Title:
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
11
Patent #:
6327183
Issue Dt:
12/04/2001
Application #:
09480868
Filing Dt:
01/10/2000
Title:
NONLINEAR STEPPED PROGRAMMING VOLTAGE
12
Patent #:
6304487
Issue Dt:
10/16/2001
Application #:
09514404
Filing Dt:
02/28/2000
Title:
Register driven means to control programming voltages
13
Patent #:
6316293
Issue Dt:
11/13/2001
Application #:
09531749
Filing Dt:
03/20/2000
Title:
A METHOD OF FORMING A NAND -TYPE FLASH MEMORY DEVICE H AVING A NON-STACKED SELECT GATE TRANSISTOR STRUCTURE
14
Patent #:
6306706
Issue Dt:
10/23/2001
Application #:
09538922
Filing Dt:
03/30/2000
Title:
Method and system for fabricating a flash memory array
15
Patent #:
6306758
Issue Dt:
10/23/2001
Application #:
09567534
Filing Dt:
05/10/2000
Title:
Multipurpose graded silicon oxynitride cap layer
16
Patent #:
6306777
Issue Dt:
10/23/2001
Application #:
09595166
Filing Dt:
06/15/2000
Title:
Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming
17
Patent #:
6303437
Issue Dt:
10/16/2001
Application #:
09632536
Filing Dt:
08/04/2000
Title:
A TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH CORNER DOPING AND SIDEWALL DOPING
18
Patent #:
6327194
Issue Dt:
12/04/2001
Application #:
09644358
Filing Dt:
08/23/2000
Title:
Precise reference wordline loading compensation for a high density flash memory device
19
Patent #:
6324108
Issue Dt:
11/27/2001
Application #:
09667891
Filing Dt:
09/22/2000
Title:
Application of external voltage during array VT testing
20
Patent #:
6320359
Issue Dt:
11/20/2001
Application #:
09671646
Filing Dt:
09/28/2000
Title:
DC-DC converter and controller and controller for detecting a malfunction therein
21
Patent #:
6310805
Issue Dt:
10/30/2001
Application #:
09676902
Filing Dt:
10/02/2000
Title:
Architecture for a dual-bank page mode memory with redundancy
22
Patent #:
6306707
Issue Dt:
10/23/2001
Application #:
09716659
Filing Dt:
11/20/2000
Title:
Double layer hard mask process to improve oxide quality for non-volatile flash memory products
23
Patent #:
6324099
Issue Dt:
11/27/2001
Application #:
09721656
Filing Dt:
11/27/2000
Title:
2-Bit/cell type nonvolatile semiconductor memory
24
Patent #:
6307784
Issue Dt:
10/23/2001
Application #:
09795856
Filing Dt:
02/28/2001
Title:
Negative gate erase
25
Patent #:
6306713
Issue Dt:
10/23/2001
Application #:
09799469
Filing Dt:
03/05/2001
Title:
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
Assignor
1
SPANSION, LLC
Exec Dt:
06/01/2015
Assignee
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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