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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12129127
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Filing Dt:
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05/29/2008
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12132636
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Filing Dt:
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06/04/2008
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Publication #:
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Pub Dt:
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12/10/2009
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Title:
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METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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12133830
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Filing Dt:
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06/05/2008
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Publication #:
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Pub Dt:
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12/10/2009
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Title:
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METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12137616
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Filing Dt:
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06/12/2008
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Publication #:
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Pub Dt:
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12/17/2009
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING PATTERN MATCHING OF INTEGRATED CIRCUIT FEATURES USING VORONOI DIAGRAMS
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12146921
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Filing Dt:
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06/26/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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COMPUTER READABLE MEDIUM, SYSTEM AND ASSOCIATED METHOD FOR DESIGNING INTEGRATED CIRCUITS WITH LOOP INSERTIONS
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12147169
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Filing Dt:
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06/26/2008
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR LAYOUT DEVICE MATCHING DRIVEN BY A SCHEMATIC EDITOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12164642
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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SYSTEMS AND METHODS INVOLVING DESIGNING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12164699
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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12166012
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Filing Dt:
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07/01/2008
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Publication #:
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Pub Dt:
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01/08/2009
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Title:
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ROUTING OF WIRES OF AN ELECTRONIC CIRCUIT
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Patent #:
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Issue Dt:
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04/14/2009
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Application #:
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12166561
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Filing Dt:
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07/02/2008
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Title:
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WIRING METHODS TO REDUCE METAL VARIATION EFFECTS ON LAUNCH-CAPTURE CLOCK PAIRS IN ORDER TO MINIMIZE CYCLE-TIME OVERLAP VIOLATIONS
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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12169447
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Filing Dt:
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07/08/2008
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Title:
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METHOD FOR HIERARCHICAL VLSI MASK LAYOUT DATA INTERROGATION
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12173217
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Filing Dt:
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07/15/2008
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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RANDOM INITIALIZATION OF LATCHES IN AN INTEGRATED CIRCUIT DESIGN FOR SIMULATION
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12173222
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Filing Dt:
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07/15/2008
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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MINIMIZING IMPACT OF DESIGN CHANGES FOR INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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12174650
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Filing Dt:
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07/17/2008
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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FUNCTIONAL VERIFICATION OF POWER GATED DESIGNS BY COMPOSITIONAL REASONING
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Patent #:
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Issue Dt:
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09/14/2010
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Application #:
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12174924
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Filing Dt:
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07/17/2008
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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IMPLEMENTING INTEGRATED CIRCUIT YIELD ESTIMATION USING VORONOI DIAGRAMS
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Patent #:
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Issue Dt:
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10/25/2011
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Application #:
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12181977
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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01/15/2009
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Title:
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TECHNIQUE FOR DETERMINING A MINIMUM SIZE OF PRESENTATION DATA
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12185943
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Filing Dt:
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08/05/2008
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Publication #:
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Pub Dt:
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02/11/2010
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Title:
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PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12191435
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Filing Dt:
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08/14/2008
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Publication #:
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Pub Dt:
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02/18/2010
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Title:
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METHOD OF MINIMIZING EARLY-MODE VIOLATIONS CAUSING MINIMUM IMPACT TO A CHIP DESIGN
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12191732
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Filing Dt:
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08/14/2008
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Publication #:
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Pub Dt:
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02/18/2010
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Title:
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APPROXIMATION OF A CLOCK GATING FUNCTION VIA BDD PATH ELIMINATION
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12196471
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Filing Dt:
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08/22/2008
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Publication #:
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Pub Dt:
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02/25/2010
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Title:
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SYSTEM AND METHODOLOGY FOR DETERMINING LAYOUT-DEPENDENT EFFECTS IN ULSI SIMULATION
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12198172
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Filing Dt:
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08/26/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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PARALLEL INTRUSION SEARCH IN HIERARCHICAL VLSI DESIGNS WITH SUBSTITUTING SCAN LINE
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12200016
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Filing Dt:
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08/28/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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HIERARCHY REASSEMBLER FOR 1XN VLSI DESIGN
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12200076
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Filing Dt:
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08/28/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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CLOSED-LOOP 1XN VLSI DESIGN SYSTEM
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12200121
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Filing Dt:
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08/28/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12201591
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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INTEGRATED DESIGN FOR MANUFACTURING FOR 1XN VLSI DESIGN
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12201643
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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TOP LEVEL HIERARCHY WIRING VIA 1XN COMPILER
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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12203038
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Filing Dt:
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09/02/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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AUTOMATICALLY CREATING MANUFACTURING TEST RULES PERTAINING TO AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12206781
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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03/11/2010
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Title:
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SYSTEM AND METHOD FOR POWER REDUCTION THROUGH POWER AWARE LATCH WEIGHTING OF COMPLEX SUB-CIRCUITS
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12206789
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
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Title:
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SYSTEM AND METHOD FOR POWER REDUCTION THROUGH POWER AWARE LATCH WEIGHTING
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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12207814
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Filing Dt:
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09/10/2008
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
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Title:
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METHOD TO GRAPHICALLY IDENTIFY REGISTERS WITH UNBALANCED SLACK AS PART OF PLACEMENT DRIVEN SYNTHESIS OPTIMIZATION
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12237482
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Filing Dt:
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09/25/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
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Title:
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METHOD FOR BOUNDED TRANSACTIONAL TIMING ANALYSIS
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12237497
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Filing Dt:
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09/25/2008
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Publication #:
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Pub Dt:
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03/26/2009
| | | | |
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Title:
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GRIDDED-ROUTER BASED WIRING ON A NON-GRIDDED LIBRARY
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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12244512
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Filing Dt:
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10/02/2008
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Publication #:
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Pub Dt:
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04/08/2010
| | | | |
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Title:
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METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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12250085
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Filing Dt:
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10/13/2008
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Publication #:
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Pub Dt:
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04/15/2010
| | | | |
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Title:
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IMPLEMENTING DIAGNOSIS OF TRANSITIONAL SCAN CHAIN DEFECTS USING LOGIC BUILT IN SELF TEST (LBIST ) TEST PATTERNS.
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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12250103
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Filing Dt:
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10/13/2008
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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IMPLEMENTING ISOLATION OF VLSI SCAN CHAIN USING ABIST TEST PATTERNS
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12262976
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Filing Dt:
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10/31/2008
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
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Title:
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VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD)
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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12269477
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Filing Dt:
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11/12/2008
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Publication #:
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Pub Dt:
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05/13/2010
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Title:
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ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12334482
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Filing Dt:
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12/14/2008
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
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Title:
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DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK BY REDUCING TARGET EDGE PAIRS USED IN DETERMINING A MANUFACTURING PENALTY OF THE LITHOGRAPHIC MASK
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12334485
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Filing Dt:
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12/14/2008
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
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Title:
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DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK BY SELECTING TARGET EDGE PAIRS USED IN DETERMINING A MANUFACTURING PENALTY OF THE LITHOGRAPHIC MASK
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12334488
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Filing Dt:
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12/14/2008
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
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Title:
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DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK USING CONTINUOUS DERIVATIVES CHARACTERIZING THE MANUFACTURABILITY ON A CONTINUOUS SCALE
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12336019
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Filing Dt:
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12/16/2008
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Publication #:
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Pub Dt:
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06/17/2010
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Title:
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SELECTIVE COMPILATION OF A SIMULATION MODEL IN VIEW OF UNAVAILABLE HIGHER LEVEL SIGNALS
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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12340072
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Filing Dt:
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12/19/2008
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Publication #:
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Pub Dt:
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06/24/2010
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Title:
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METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING
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Patent #:
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Issue Dt:
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08/14/2012
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Application #:
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12347968
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Filing Dt:
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12/31/2008
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Publication #:
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Pub Dt:
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08/27/2009
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Title:
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STRUCTURE FOR DETECTING CLOCK GATING OPPORTUNITIES IN A PIPELINED ELECTRONIC CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12349104
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Filing Dt:
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01/06/2009
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Publication #:
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Pub Dt:
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07/08/2010
| | | | |
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Title:
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EFFICIENT ISOTROPIC MODELING APPROACH TO INCORPORATE ELECTROMAGNETIC EFFECTS INTO LITHOGRAPHIC PROCESS SIMULATIONS
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12349108
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Filing Dt:
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01/06/2009
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Publication #:
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Pub Dt:
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07/08/2010
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Title:
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FAST AND ACCURATE METHOD TO SIMULATE INTERMEDIATE RANGE FLARE EFFECTS
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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12351944
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Filing Dt:
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01/12/2009
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Publication #:
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Pub Dt:
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07/15/2010
| | | | |
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Title:
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METHOD AND SYSTEM FOR EFFICIENT VALIDATION OF CLOCK SKEWS DURING HIERARCHICAL STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12351950
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Filing Dt:
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01/12/2009
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Publication #:
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Pub Dt:
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07/15/2010
| | | | |
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Title:
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SCAN CHAIN FAIL DIAGNOSTICS
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12354306
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Filing Dt:
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01/15/2009
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Publication #:
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Pub Dt:
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07/15/2010
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Title:
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METHOD OF PERFORMING TIMING ANALYSIS ON INTEGRATED CIRCUIT CHIPS WITH CONSIDERATION OF PROCESS VARIATIONS
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12354360
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Filing Dt:
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01/15/2009
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Publication #:
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Pub Dt:
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07/15/2010
| | | | |
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Title:
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METHOD FOR EFFICIENTLY CHECKPOINTING AND RESTARTING STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12356116
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Filing Dt:
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01/20/2009
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Publication #:
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Pub Dt:
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07/22/2010
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Title:
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SYSTEM FOR QUICKLY SPECIFYING FORMAL VERIFICATION ENVIRONMENTS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12358793
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Filing Dt:
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01/23/2009
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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MINTERM TRACING AND REPORTING
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12362513
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Filing Dt:
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01/30/2009
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
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Title:
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AUTOMATED USE OF UNINTERPRETED FUNCTIONS IN SEQUENTIAL EQUIVALENCE
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12363340
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Filing Dt:
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01/30/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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METHOD AND SYSTEM FOR POINT-TO-POINT FAST DELAY ESTIMATION FOR VLSI CIRCUITS
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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12392278
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Filing Dt:
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02/25/2009
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Publication #:
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Pub Dt:
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08/26/2010
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Title:
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METHOD AND SYSTEM FOR SEQUENTIAL NETLIST REDUCTION THROUGH TRACE-CONTAINMENT
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12395373
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Filing Dt:
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02/27/2009
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Publication #:
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Pub Dt:
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09/02/2010
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Title:
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TECHNIQUES FOR PARALLEL BUFFER INSERTION
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12410962
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Filing Dt:
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03/25/2009
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Publication #:
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Pub Dt:
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09/30/2010
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Title:
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METHOD, SYSTEM AND APPLICATION FOR SEQUENTIAL COFACTOR-BASED ANALYSIS OF NETLISTS
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Patent #:
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Issue Dt:
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04/03/2012
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Application #:
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12416222
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Filing Dt:
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04/01/2009
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12416232
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Filing Dt:
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04/01/2009
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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ENHANCING FORMAL DESIGN VERIFICATION BY REUSING PREVIOUS RESULTS
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12420156
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Filing Dt:
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04/08/2009
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Publication #:
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Pub Dt:
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10/14/2010
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Title:
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IMPROVED OBJECT PLACEMENT IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12420891
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Filing Dt:
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04/09/2009
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Publication #:
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Pub Dt:
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10/14/2010
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Title:
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INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12423387
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Filing Dt:
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04/14/2009
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Publication #:
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Pub Dt:
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10/14/2010
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Title:
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ACCURATE APPROXIMATION OF RESISTANCE IN A WIRE WITH IRREGULAR BIASING AND DETERMINATION OF INTERCONNECT CAPACITANCES IN VLSI LAYOUTS IN THE PRESENCE OF CATASTROPHIC OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12425095
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Filing Dt:
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04/16/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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TRACE CONTAINMENT DETECTION OF COMBINATIONAL DESIGNS VIA CONSTRAINT-BASED UNCORRELATED EQUIVALENCE CHECKING
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Patent #:
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Issue Dt:
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02/07/2012
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Application #:
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12426342
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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METHOD AND SYSTEM FOR SELECTIVE STRESS ENABLEMENT IN SIMULATION MODELING
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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12426492
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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METHOD OF EMPLOYING SLEW DEPENDENT PIN CAPACITANCES TO CAPTURE INTERCONNECT PARASITICS DURING TIMING ABSTRACTION OF VLSI CIRCUITS
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12431865
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Filing Dt:
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04/29/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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METHOD FOR FORMING ARBITRARY LITHOGRAPHIC WAVEFRONTS USING STANDARD MASK TECHNOLOGY
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12463742
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Filing Dt:
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05/11/2009
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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HIGH CONTRAST LITHOGRAPHIC MASKS
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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12467326
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Filing Dt:
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05/18/2009
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12471653
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Filing Dt:
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05/26/2009
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Publication #:
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Pub Dt:
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12/02/2010
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Title:
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ORDER INDEPENDENT METHOD OF PERFORMING STATISTICAL N-WAY MAXIMUM/MINIMUM OPERATION FOR NON-GAUSSIAN AND NON-LINEAR DISTRIBUTIONS
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12484293
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Filing Dt:
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06/15/2009
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Publication #:
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Pub Dt:
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12/16/2010
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Title:
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DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12489441
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Filing Dt:
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06/23/2009
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Publication #:
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Pub Dt:
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12/23/2010
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Title:
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CLOCK GATING USING ABSTRACTION REFINEMENT
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12538229
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Filing Dt:
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08/10/2009
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Publication #:
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Pub Dt:
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02/10/2011
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Title:
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SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12549061
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Filing Dt:
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08/27/2009
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Publication #:
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Pub Dt:
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03/03/2011
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Title:
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TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12557623
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Filing Dt:
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09/11/2009
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Publication #:
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Pub Dt:
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03/17/2011
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Title:
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AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED SCAN DESIGN
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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12557872
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Filing Dt:
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09/11/2009
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Publication #:
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Pub Dt:
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03/17/2011
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Title:
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METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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12580373
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Filing Dt:
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10/16/2009
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Publication #:
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Pub Dt:
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04/21/2011
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Title:
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TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12603594
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Filing Dt:
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10/22/2009
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Publication #:
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Pub Dt:
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04/28/2011
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Title:
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GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12619742
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Filing Dt:
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11/17/2009
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Publication #:
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Pub Dt:
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05/19/2011
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Title:
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SIMULTANEOUS PHOTOLITHOGRAPHIC MASK AND TARGET OPTIMIZATION
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12652409
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Filing Dt:
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01/05/2010
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Publication #:
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Pub Dt:
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07/07/2011
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Title:
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AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12685803
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01/12/2010
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Publication #:
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Pub Dt:
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07/14/2011
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Title:
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REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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12771613
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Filing Dt:
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04/30/2010
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Pub Dt:
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11/03/2011
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Title:
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ENHANCED ANALYSIS OF ARRAY-BASED NETLISTS VIA REPARAMETERIZATION
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Patent #:
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Issue Dt:
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03/27/2012
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12771677
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04/30/2010
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Pub Dt:
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11/03/2011
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Title:
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EFFICIENT REDUNDANCY IDENTIFICATION, REDUNDANCY REMOVAL, AND SEQUENTIAL EQUIVALENCE CHECKING WITHIN DESIGNS INCLUDING MEMORY ARRAYS
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10/16/2012
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12775633
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05/07/2010
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Pub Dt:
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11/10/2011
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Title:
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ARRAY CONCATENATION IN AN INTEGRATED CIRCUIT DESIGN
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08/07/2012
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13080148
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04/05/2011
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Pub Dt:
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07/28/2011
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Title:
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SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN
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Issue Dt:
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10/30/2012
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13100584
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05/04/2011
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Pub Dt:
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09/15/2011
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Title:
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COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE
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Issue Dt:
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03/13/2012
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Application #:
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13102249
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05/06/2011
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09/01/2011
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Title:
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METHOD FOR TESTING INTEGRATED CIRCUITS
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Issue Dt:
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03/13/2012
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13187201
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07/20/2011
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Pub Dt:
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11/17/2011
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Title:
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EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS
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Patent #:
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Issue Dt:
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08/07/2012
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13216362
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08/24/2011
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Pub Dt:
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12/15/2011
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Title:
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METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
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Issue Dt:
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08/06/2013
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13344178
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01/05/2012
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05/03/2012
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Title:
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RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS
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Issue Dt:
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11/11/2014
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13364249
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02/01/2012
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07/26/2012
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Title:
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COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
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Issue Dt:
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05/27/2014
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13364256
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02/01/2012
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07/26/2012
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Title:
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COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
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04/23/2013
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13471789
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05/15/2012
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Pub Dt:
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09/06/2012
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Title:
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METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
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07/09/2013
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13517811
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06/14/2012
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10/04/2012
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Title:
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SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN
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