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Reel/Frame:013091/0156   Pages: 8
Recorded: 07/11/2002
Conveyance: RE-RECORD TO CORRECT THE NAMES OF THE SEVENTH AND EIGHT INVENTORS ON REEL 012509 FRAME 0033. ASSIGNORS CONFIRM THE ASSIGNMENT OF THE ENTIRE INTEREST.
Total properties: 1
1
Patent #:
6544824
Issue Dt:
04/08/2003
Application #:
10038390
Filing Dt:
01/03/2002
Title:
METHOD TO FORM A VERTICAL TRANSISTOR BY FIRST FORMING A GATE/SPACER STACK, THEN USING SELECTIVE EPITAXY TO FORM SOURCE, DRAIN AND CHANNEL
Assignors
1
PRADEEP, YELEHANKA RAMACHANDRAMURTHY
Exec Dt:
10/26/2001
2
ZHENG, JIA ZHEN
Exec Dt:
10/26/2001
3
CHAN, LAP
Exec Dt:
10/26/2001
4
QUEK, ELGIN
Exec Dt:
10/26/2001
5
SUNDARESAN, RAVI
Exec Dt:
10/26/2001
6
PAN, YANG
Exec Dt:
10/26/2001
7
LEE, JAMES YONG MENG
Exec Dt:
10/26/2001
8
KEUNG, YING LEUNG
Exec Dt:
10/26/2001
Assignee
1
CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2
SINGAPORE, SINGAPORE 73840
Correspondence name and address
GEORGE O. SAILE
20 MCINTOSH DRIVE
POUGHKEEPSIE, NY 12603

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