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Patent Assignment Details
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Reel/Frame:024651/0158   Pages: 6
Recorded: 07/08/2010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 19
1
Patent #:
Issue Dt:
12/07/2004
Application #:
10112833
Filing Dt:
03/29/2002
Title:
SEMICONDUCTOR TOPOGRAPHY WITH A FILL MATERIAL ARANGED WITHIN A PLURALITY OF VALLEYS ASSOCIATED WITH THE SURFACE ROUGHNESS OF THE METAL LAYER
2
Patent #:
Issue Dt:
05/25/2004
Application #:
10113309
Filing Dt:
03/29/2002
Title:
SMOOTH METAL SEMICONDUCTOR SURFACE AND METHOD FOR MAKING THE SAME
3
Patent #:
Issue Dt:
12/06/2005
Application #:
10122737
Filing Dt:
04/15/2002
Title:
METAL ETCH PROCESS SELECTIVE TO METALLIC INSULATING MATERIALS
4
Patent #:
Issue Dt:
07/26/2005
Application #:
10175628
Filing Dt:
06/20/2002
Title:
DIE SURFACE MAGNETIC FIELD SHIELD
5
Patent #:
Issue Dt:
05/10/2005
Application #:
10184673
Filing Dt:
06/28/2002
Title:
MRAM FIELD-INDUCING LAYER CONFIGURATION
6
Patent #:
Issue Dt:
11/23/2004
Application #:
10241040
Filing Dt:
09/11/2002
Title:
LOCALIZED FIELD-INDUCING LINE AND METHOD FOR MAKING THE SAME
7
Patent #:
Issue Dt:
08/10/2004
Application #:
10277340
Filing Dt:
10/22/2002
Title:
MEMORY CIRCUIT WITH SELECTIVE ADDRESS PATH
8
Patent #:
Issue Dt:
03/01/2005
Application #:
10281601
Filing Dt:
10/28/2002
Title:
MRAM DATA LINE CONFIGURATION AND METHOD OF OPERATION
9
Patent #:
Issue Dt:
11/02/2004
Application #:
10300137
Filing Dt:
11/20/2002
Title:
METHOD FOR DEPOSITING SILICON NITRIDE
10
Patent #:
Issue Dt:
05/17/2005
Application #:
10309380
Filing Dt:
12/03/2002
Title:
METHOD FOR OXIDIZING A METAL LAYER
11
Patent #:
Issue Dt:
07/06/2004
Application #:
10319318
Filing Dt:
12/13/2002
Title:
METHOD FOR PLASMA ETCHING A MICROELECTRONIC TOPOGRAPHY USING A PULSE BIAS POWER
12
Patent #:
Issue Dt:
10/28/2003
Application #:
10321035
Filing Dt:
12/17/2002
Title:
LOCALIZED MRAM DATA LINE AND METHOD OF OPERATION
13
Patent #:
Issue Dt:
08/22/2006
Application #:
10325008
Filing Dt:
12/20/2002
Title:
MAGNETIC MEMORY ARRAY WITH AN IMPROVED WORD LINE CONFIGURATION
14
Patent #:
Issue Dt:
06/06/2006
Application #:
10699155
Filing Dt:
10/31/2003
Title:
MAGNETIC MEMORY ARRAY CONFIGURATION
15
Patent #:
Issue Dt:
07/25/2006
Application #:
10745725
Filing Dt:
12/24/2003
Title:
NON-VOLATILE LATCH WITH MAGNETIC JUNCTIONS
16
Patent #:
Issue Dt:
04/03/2007
Application #:
10786440
Filing Dt:
02/25/2004
Publication #:
Pub Dt:
09/09/2004
Title:
MAGNETIC MEMORY CELL JUNCTION AND METHOD FOR FORMING A MAGNETIC MEMORY CELL JUNCTION
17
Patent #:
Issue Dt:
10/16/2007
Application #:
10809134
Filing Dt:
03/24/2004
Title:
MAGNETIC MEMORY ARRAY ARCHITECTURE
18
Patent #:
Issue Dt:
02/12/2008
Application #:
10850247
Filing Dt:
05/20/2004
Title:
SMOOTH METAL SEMICONDUCTOR SURFACE AND METHOD FOR MAKING THE SAME
19
Patent #:
Issue Dt:
04/17/2007
Application #:
11039301
Filing Dt:
01/19/2005
Title:
METHODS FOR FABRICATING MAGNETIC CELL JUNCTIONS AND A STRUCTURE RESULTING AND/OR USED FOR SUCH METHODS
Assignor
1
Exec Dt:
07/08/2010
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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