|
|
|
|
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Patent #:
|
|
Issue Dt:
|
09/27/2005
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Application #:
|
10721643
|
Filing Dt:
|
11/24/2003
|
|
Title:
|
READING FLASH MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10726508
|
Filing Dt:
|
12/04/2003
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|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
FLASH MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10726829
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Filing Dt:
|
12/03/2003
|
|
Title:
|
POST CMP PRECURSOR TREATMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10726868
|
Filing Dt:
|
12/03/2003
|
|
Title:
|
DIELECTRIC PATTERN FORMATION FOR ORGANIC ELECTRONIC DEVICES
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|
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|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10727481
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
METHOD FOR STORING IN NONVOLATILE MEMORY AND STORAGE UNIT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10728510
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Filing Dt:
|
12/05/2003
|
|
Title:
|
NEUTRON DETECTING DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10729732
|
Filing Dt:
|
12/05/2003
|
|
Title:
|
HARD MASK SPACER FOR SUBLITHOGRAPHIC BITLINE
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|
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|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10731494
|
Filing Dt:
|
12/09/2003
|
|
Title:
|
PROCESS FOR FABRICATION OF SPACER LAYER WITH REDUCED HYDROGEN CONTENT IN SEMICONDUCTOR DEVICE
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|
|
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|
Patent #:
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|
Issue Dt:
|
10/18/2005
|
Application #:
|
10731659
|
Filing Dt:
|
12/09/2003
|
|
Title:
|
PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
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|
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|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10738301
|
Filing Dt:
|
12/16/2003
|
|
Title:
|
METHOD AND DEVICE FOR PROGRAMMING CELLS IN A MEMORY ARRAY IN A NARROW DISTRIBUTION
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Patent #:
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|
Issue Dt:
|
10/30/2007
|
Application #:
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10738322
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Filing Dt:
|
12/16/2003
|
|
Title:
|
FLASH MEMORY WITH BURIED BIT LINES
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|
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|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10747692
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10754948
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Filing Dt:
|
01/08/2004
|
|
Title:
|
INTEGRATED ONO PROCESSING FOR SEMICONDUCTOR DEVICES USING IN-SITU STEAM GENERATION (ISSG) PROCESS
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|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10755430
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Filing Dt:
|
01/12/2004
|
|
Title:
|
NARROW BITLINE USING SAFIER FOR MIRRORBIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10755740
|
Filing Dt:
|
01/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2005
| | | | |
|
Title:
|
POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
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|
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|
Patent #:
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|
Issue Dt:
|
04/04/2006
|
Application #:
|
10755979
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Filing Dt:
|
01/12/2004
|
|
Title:
|
SUBSTRATE BIAS FOR PROGRAMMING NON-VOLATILE MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10756573
|
Filing Dt:
|
01/12/2004
|
|
Title:
|
HIGH VOLTAGE TRANSISTOR SCALING TILT ION IMPLANT METHOD
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/01/2007
|
Application #:
|
10756585
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Filing Dt:
|
01/12/2004
|
|
Title:
|
METHOD AND STRUCTURE FOR CONTROLLING FLOATING BODY EFFECTS
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|
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
10758148
|
Filing Dt:
|
01/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2005
| | | | |
|
Title:
|
Efficient use of wafer area with device under the pad approach
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10758173
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Filing Dt:
|
01/14/2004
|
|
Title:
|
ELECTROSTATIC DISCHARGE PERFORMANCE OF A SILICON STRUCTURE AND EFFICIENT USE OF AREA WITH ELECTROSTATIC DISCHARGE PROTECTIVE DEVICE UNDER THE PAD APPROACH AND ADJUSTMENT OF VIA CONFIGURATION THERETO TO CONTROL DRAIN JUNCTION RESISTANCE
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|
|
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Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10759809
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Filing Dt:
|
01/16/2004
|
|
Title:
|
STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD
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|
|
|
Patent #:
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|
Issue Dt:
|
04/11/2006
|
Application #:
|
10759855
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Filing Dt:
|
01/16/2004
|
|
Title:
|
FLEXIBLE CASCODE AMPLIFIER CIRCUIT WITH HIGH GAIN FOR FLASH MEMORY CELLS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/16/2004
|
Application #:
|
10762071
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Filing Dt:
|
01/20/2004
|
|
Title:
|
METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10762445
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Filing Dt:
|
01/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR LOW VSS RESISTANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/17/2006
|
Application #:
|
10768188
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10770010
|
Filing Dt:
|
02/03/2004
|
|
Title:
|
NON -VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10770245
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
DISPOSABLE HARD MASK FOR MEMORY BITLINE SCALING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10770260
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
FLASH MEMORY CELL WITH UV PROTECTIVE LAYER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10770673
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
BITLINE HARD MASK SPACER FLOW FOR MEMORY CELL SCALING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10776850
|
Filing Dt:
|
02/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10776870
|
Filing Dt:
|
02/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
ACTIVE PROGRAMMING AND OPERATION OF A MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10791417
|
Filing Dt:
|
03/02/2004
|
|
Title:
|
TESTING FOR OPERATING LIFE OF A MEMORY DEVICE WITH ADDRESS CYCLING USING A GRAY CODE SEQUENCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10795890
|
Filing Dt:
|
03/08/2004
|
|
Title:
|
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10795924
|
Filing Dt:
|
03/08/2004
|
|
Title:
|
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10799413
|
Filing Dt:
|
03/12/2004
|
|
Title:
|
AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/27/2006
|
Application #:
|
10812703
|
Filing Dt:
|
03/30/2004
|
|
Title:
|
RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10817131
|
Filing Dt:
|
04/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
In-situ surface treatment for memory cell formation
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10817186
|
Filing Dt:
|
04/02/2004
|
|
Title:
|
USING ORGANIC SEMICONDUCTOR MEMORY IN CONJUNCTION WITH A MEMS ACTUATOR FOR AN ULTRA HIGH DENSITY MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
10817467
|
Filing Dt:
|
04/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
POLYMER DIELECTRICS FOR MEMORY ELEMENT ARRAY INTERCONNECT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10818112
|
Filing Dt:
|
04/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10818261
|
Filing Dt:
|
04/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10819162
|
Filing Dt:
|
04/07/2004
|
|
Title:
|
FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10821312
|
Filing Dt:
|
04/08/2004
|
|
Title:
|
NARROW WIDE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
10823970
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10823972
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
MEMORY DEVICE WITH AN ALTERNATING VSS INTERCONNECTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10835341
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
METHOD FOR PROVIDING SHORT CHANNEL EFFECT CONTROL USING A SILICIDE VSS LINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10838215
|
Filing Dt:
|
05/05/2004
|
|
Title:
|
FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
10838962
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10839561
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10839562
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10839614
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10839626
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
MEMORY ARRAY WITH MEMORY CELLS HAVING REDUCED SHORT CHANNEL EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10841850
|
Filing Dt:
|
05/07/2004
|
|
Title:
|
FLASH MEMORY CELL AND METHODS FOR PROGRAMMING AND ERASING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10841933
|
Filing Dt:
|
05/06/2004
|
|
Title:
|
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10843289
|
Filing Dt:
|
05/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
BITLINE IMPLANT UTILIZING DUAL POLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10844116
|
Filing Dt:
|
05/12/2004
|
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10848679
|
Filing Dt:
|
05/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10859369
|
Filing Dt:
|
06/01/2004
|
|
Title:
|
METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10860450
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
08/15/2006
|
Application #:
|
10861437
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10861575
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
02/13/2007
|
Application #:
|
10862636
|
Filing Dt:
|
06/07/2004
|
|
Title:
|
LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10863673
|
Filing Dt:
|
06/08/2004
|
|
Title:
|
MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10863933
|
Filing Dt:
|
06/09/2004
|
|
Title:
|
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10864142
|
Filing Dt:
|
06/08/2004
|
|
Title:
|
MEMORY WORDLINE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10864947
|
Filing Dt:
|
06/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10869286
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10869774
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10873069
|
Filing Dt:
|
06/21/2004
|
|
Title:
|
ELECTRICALLY ADDRESSABLE MEMORY SWITCH
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10878091
|
Filing Dt:
|
06/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
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Title:
|
MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10882538
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Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10883350
|
Filing Dt:
|
07/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
|
Title:
|
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10883924
|
Filing Dt:
|
07/01/2004
|
|
Title:
|
FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10885284
|
Filing Dt:
|
07/06/2004
|
|
Title:
|
ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10885944
|
Filing Dt:
|
07/07/2004
|
|
Title:
|
CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10887585
|
Filing Dt:
|
07/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
|
Title:
|
BOND PAD STRUCTURE FOR COPPER METALLIZATION HAVING INCREASED RELIABILITY AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10887782
|
Filing Dt:
|
07/09/2004
|
|
Title:
|
METHOD OF REFERENCE CELL DESIGN FOR OPTIMIZED MEMORY CIRCUIT YIELD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10889424
|
Filing Dt:
|
07/12/2004
|
|
Title:
|
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10896292
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10896299
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10899344
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10899684
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10899873
|
Filing Dt:
|
07/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
MOLECULAR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10900832
|
Filing Dt:
|
07/28/2004
|
|
Title:
|
METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10909693
|
Filing Dt:
|
08/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10915771
|
Filing Dt:
|
08/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
|
Title:
|
MEMORY CELL WITH REDUCED DIBL AND VSS RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
10916167
|
Filing Dt:
|
08/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
|
Title:
|
METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10917562
|
Filing Dt:
|
08/13/2004
|
|
Title:
|
USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10919119
|
Filing Dt:
|
08/16/2004
|
|
Title:
|
TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10919572
|
Filing Dt:
|
08/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
|
Title:
|
POLYMER MEMORY DEVICE WITH VARIABLE PERIOD OF RETENTION TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10919846
|
Filing Dt:
|
08/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR ADJUSTING PROGRAMMING THRESHOLDS OF POLYMER MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10919872
|
Filing Dt:
|
08/17/2004
|
|
Title:
|
METHOD TO IMPROVE YIELD AND SIMPLIFY OPERATION OF POLYMER MEMORY CELLS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10928354
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
Deposition of hard-mask with minimized hillocks and bubbles
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10928582
|
Filing Dt:
|
08/27/2004
|
|
Title:
|
SONOS MEMORY WITH INVERSION BIT-LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
10928665
|
Filing Dt:
|
08/27/2004
|
|
Title:
|
SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10933588
|
Filing Dt:
|
09/03/2004
|
|
Title:
|
SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
10934828
|
Filing Dt:
|
09/02/2004
|
|
Title:
|
SEMICONDUCTOR FORMATION METHOD THAT UTILIZES MULTIPLE ETCH STOP LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10934923
|
Filing Dt:
|
09/02/2004
|
|
Title:
|
SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10935301
|
Filing Dt:
|
09/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
|
Title:
|
Vertical JFET as used for selective component in a memory array
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10939773
|
Filing Dt:
|
09/13/2004
|
|
Title:
|
METHOD AND STRUCTURE OF MEMORY ELEMENT PLUG WITH CONDUCTIVE TA REMOVED FROM SIDEWALL AT REGION OF MEMORY ELEMENT FILM
|
|
