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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036711/0160   Pages: 27
Recorded: 09/29/2015
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 340
Page 4 of 4
Pages: 1 2 3 4
1
Patent #:
NONE
Issue Dt:
Application #:
13103952
Filing Dt:
05/09/2011
Publication #:
US20110219245
Pub Dt:
09/08/2011
Title:
ADAPTIVE POWER CONTROL
2
Patent #:
NONE
Issue Dt:
Application #:
13113798
Filing Dt:
05/23/2011
Publication #:
US20110221029
Pub Dt:
09/15/2011
Title:
BALANCED ADAPTIVE BODY BIAS CONTROL
3
Patent #:
NONE
Issue Dt:
Application #:
13118762
Filing Dt:
05/31/2011
Publication #:
US20110231678
Pub Dt:
09/22/2011
Title:
ADAPTIVE POWER CONTROL BASED ON POST PACKAGE CHARACTERIZATION OF INTEGRATED CIRCUITS
4
Patent #:
8549266
Issue Dt:
10/01/2013
Application #:
13155291
Filing Dt:
06/07/2011
Publication #:
US20110238961
Pub Dt:
09/29/2011
Title:
SYSTEM AND METHOD OF INSTRUCTION MODIFICATION
5
Patent #:
8359443
Issue Dt:
01/22/2013
Application #:
13165560
Filing Dt:
06/21/2011
Publication #:
US20120159104
Pub Dt:
06/21/2012
Title:
SECURE MEMORY ACCESS SYSTEM AND METHOD
6
Patent #:
8370604
Issue Dt:
02/05/2013
Application #:
13168800
Filing Dt:
06/24/2011
Publication #:
US20120166703
Pub Dt:
06/28/2012
Title:
METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES
7
Patent #:
8330515
Issue Dt:
12/11/2012
Application #:
13168894
Filing Dt:
06/24/2011
Publication #:
US20120161839
Pub Dt:
06/28/2012
Title:
INVERTING ZIPPER REPEATER CIRCUIT
8
Patent #:
8370785
Issue Dt:
02/05/2013
Application #:
13168896
Filing Dt:
06/24/2011
Publication #:
US20110258590
Pub Dt:
10/20/2011
Title:
SOFTWARE CONTROLLED TRANSISTOR BODY BIAS
9
Patent #:
8298896
Issue Dt:
10/30/2012
Application #:
13214593
Filing Dt:
08/22/2011
Publication #:
US20110300681
Pub Dt:
12/08/2011
Title:
FORMATION OF A SUPER STEEP RETROGRADE CHANNEL
10
Patent #:
8464033
Issue Dt:
06/11/2013
Application #:
13221812
Filing Dt:
08/30/2011
Publication #:
US20120079257
Pub Dt:
03/29/2012
Title:
SETTING A FLAG BIT TO DEFER EVENT HANDLING TO ONE OF MULTIPLE SAFE POINTS IN AN INSTRUCTION STREAM
11
Patent #:
8508262
Issue Dt:
08/13/2013
Application #:
13227166
Filing Dt:
09/07/2011
Publication #:
US20110316597
Pub Dt:
12/29/2011
Title:
SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY
12
Patent #:
8593169
Issue Dt:
11/26/2013
Application #:
13235301
Filing Dt:
09/16/2011
Publication #:
US20120001651
Pub Dt:
01/05/2012
Title:
FREQUENCY SPECIFIC CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS
13
Patent #:
8451025
Issue Dt:
05/28/2013
Application #:
13236554
Filing Dt:
09/19/2011
Publication #:
US20120242387
Pub Dt:
09/27/2012
Title:
ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT
14
Patent #:
8341329
Issue Dt:
12/25/2012
Application #:
13242070
Filing Dt:
09/23/2011
Publication #:
US20120017032
Pub Dt:
01/19/2012
Title:
METHOD AND SYSTEM FOR PROVIDING HARDWARE SUPPORT FOR MEMORY PROTECTION AND VIRTUAL MEMORY ADDRESS TRANSLATION FOR A VIRTUAL MACHINE
15
Patent #:
8719544
Issue Dt:
05/06/2014
Application #:
13243943
Filing Dt:
09/23/2011
Publication #:
US20120110306
Pub Dt:
05/03/2012
Title:
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
16
Patent #:
9222843
Issue Dt:
12/29/2015
Application #:
13243976
Filing Dt:
09/23/2011
Publication #:
US20120013364
Pub Dt:
01/19/2012
Title:
SYSTEM FOR ON-CHIP TEMPERATURE MEASUREMENT IN INTEGRATED CIRCUITS
17
Patent #:
8587344
Issue Dt:
11/19/2013
Application #:
13356396
Filing Dt:
01/23/2012
Publication #:
US20120242371
Pub Dt:
09/27/2012
Title:
POWER EFFICIENT MULTIPLEXER
18
Patent #:
8516224
Issue Dt:
08/20/2013
Application #:
13362863
Filing Dt:
01/31/2012
Publication #:
US20120166768
Pub Dt:
06/28/2012
Title:
PIPELINE REPLAY SUPPORT FOR MULTICYCLE OPERATIONS
19
Patent #:
8607025
Issue Dt:
12/10/2013
Application #:
13363050
Filing Dt:
01/31/2012
Publication #:
US20120131307
Pub Dt:
05/24/2012
Title:
DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES
20
Patent #:
NONE
Issue Dt:
Application #:
13370241
Filing Dt:
02/09/2012
Publication #:
US20120210155
Pub Dt:
08/16/2012
Title:
STORING CONTEXT INFORMATION PRIOR TO NOT SUPPLYING POWER TO A PROCESSOR
21
Patent #:
8458496
Issue Dt:
06/04/2013
Application #:
13406434
Filing Dt:
02/27/2012
Publication #:
US20120166849
Pub Dt:
06/28/2012
Title:
SYSTEMS AND METHODS FOR CONTROL OF INTEGRATED CIRCUITS COMPRISING BODY BIASING SYSTEMS
22
Patent #:
8458437
Issue Dt:
06/04/2013
Application #:
13411469
Filing Dt:
03/02/2012
Publication #:
US20120246413
Pub Dt:
09/27/2012
Title:
SUPPORTING MULTIPLE BYTE ORDER FORMATS IN A COMPUTER SYSTEM
23
Patent #:
8629711
Issue Dt:
01/14/2014
Application #:
13461588
Filing Dt:
05/01/2012
Publication #:
US20120212285
Pub Dt:
08/23/2012
Title:
PRECISE CONTROL COMPONENT FOR A SUBSTARATE POTENTIAL REGULATION CIRCUIT
24
Patent #:
9081563
Issue Dt:
07/14/2015
Application #:
13488138
Filing Dt:
06/04/2012
Publication #:
US20120246453
Pub Dt:
09/27/2012
Title:
METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR
25
Patent #:
9652244
Issue Dt:
05/16/2017
Application #:
13532517
Filing Dt:
06/25/2012
Publication #:
US20120265965
Pub Dt:
10/18/2012
Title:
PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD
26
Patent #:
9100003
Issue Dt:
08/04/2015
Application #:
13550459
Filing Dt:
07/16/2012
Publication #:
US20120281483
Pub Dt:
11/08/2012
Title:
SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE
27
Patent #:
9407241
Issue Dt:
08/02/2016
Application #:
13587827
Filing Dt:
08/16/2012
Publication #:
US20120319721
Pub Dt:
12/20/2012
Title:
CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS
28
Patent #:
8566564
Issue Dt:
10/22/2013
Application #:
13714328
Filing Dt:
12/13/2012
Publication #:
US20130111184
Pub Dt:
05/02/2013
Title:
METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES
29
Patent #:
8601229
Issue Dt:
12/03/2013
Application #:
13714351
Filing Dt:
12/13/2012
Publication #:
US20130103915
Pub Dt:
04/25/2013
Title:
SECURE MEMORY ACCESS SYSTEM AND METHOD
30
Patent #:
8549211
Issue Dt:
10/01/2013
Application #:
13714356
Filing Dt:
12/13/2012
Publication #:
US20130103882
Pub Dt:
04/25/2013
Title:
METHOD AND SYSTEM FOR PROVIDING HARDWARE SUPPORT FOR MEMORY PROTECTION AND VIRTUAL MEMORY ADDRESS TRANSLATION FOR A VIRTUAL MACHINE
31
Patent #:
8806247
Issue Dt:
08/12/2014
Application #:
13725901
Filing Dt:
12/21/2012
Publication #:
US20130132749
Pub Dt:
05/23/2013
Title:
ADAPTIVE POWER CONTROL
32
Patent #:
9026810
Issue Dt:
05/05/2015
Application #:
13731491
Filing Dt:
12/31/2012
Publication #:
US20140013127
Pub Dt:
01/09/2014
Title:
ADAPTIVE CONTROL OF OPERATING AND BODY BIAS VOLTAGES
33
Patent #:
8898616
Issue Dt:
11/25/2014
Application #:
13741246
Filing Dt:
01/14/2013
Publication #:
US20140033160
Pub Dt:
01/30/2014
Title:
SOFTWARE CONTROLLED TRANSISTOR BODY BIAS
34
Patent #:
NONE
Issue Dt:
Application #:
13950495
Filing Dt:
07/25/2013
Publication #:
US20130311802
Pub Dt:
11/21/2013
Title:
MAINTAINING PROCESSOR CONTEXT BEFORE ENTERING POWER SAVING MODE
35
Patent #:
8924648
Issue Dt:
12/30/2014
Application #:
14033314
Filing Dt:
09/20/2013
Title:
METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES
36
Patent #:
9160321
Issue Dt:
10/13/2015
Application #:
14083348
Filing Dt:
11/18/2013
Publication #:
US20140070848
Pub Dt:
03/13/2014
Title:
POWER EFFICIENT MULTIPLEXER
37
Patent #:
9548725
Issue Dt:
01/17/2017
Application #:
14091255
Filing Dt:
11/26/2013
Publication #:
US20140084968
Pub Dt:
03/27/2014
Title:
FREQUENCY SPECIFIC CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS
38
Patent #:
10061582
Issue Dt:
08/28/2018
Application #:
14143926
Filing Dt:
12/30/2013
Publication #:
US20140115305
Pub Dt:
04/24/2014
Title:
METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION
39
Patent #:
9406601
Issue Dt:
08/02/2016
Application #:
14160200
Filing Dt:
01/21/2014
Publication #:
US20140131833
Pub Dt:
05/15/2014
Title:
BODY-BIAS VOLTAGE ROUTING STRUCTURES
40
Patent #:
9558116
Issue Dt:
01/31/2017
Application #:
14295062
Filing Dt:
06/03/2014
Publication #:
US20140289471
Pub Dt:
09/25/2014
Title:
COHERENCE DE-COUPLING BUFFER
Assignor
1
INTELLECTUAL VENTURE FUNDING LLC
Exec Dt:
08/27/2015
Assignee
1
INTELLECTUAL VENTURES HOLDING 81 LLC
7251 W LAKE MEAD BLVD
STE 300
LAS VEGAS, NEVADA 89128
Correspondence name and address
MURABITO, HAO & BARNES LLP
TWO NORTH MARKET STREET
THIRD FLOOR
SAN JOSE, CA 95113

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