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Reel/Frame:	052561/0161			Pages:	20
		Recorded:	05/04/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 316
Page 2 of 4
Pages: 1 2 3 4

Patent #:	9443767	Issue Dt:	09/13/2016	Application #:	14571700	Filing Dt:	12/16/2014
Publication #:	US20160172249	Pub Dt:	06/16/2016
Title:	DESIGN STRUCTURE FOR METAL OXIDE SEMICONDUCTOR CAPACITOR

Patent #:	9653534	Issue Dt:	05/16/2017	Application #:	14572974	Filing Dt:	12/17/2014
Publication #:	US20160181353	Pub Dt:	06/23/2016
Title:	TRENCH METAL-INSULATOR-METAL CAPACITOR WITH OXYGEN GETTERING LAYER

Patent #:	9530701	Issue Dt:	12/27/2016	Application #:	14575602	Filing Dt:	12/18/2014
Publication #:	US20160181164	Pub Dt:	06/23/2016
Title:	METHOD OF FORMING SEMICONDUCTOR FINS ON SOI SUBSTRATE

Patent #:	9299686	Issue Dt:	03/29/2016	Application #:	14598352	Filing Dt:	01/16/2015
Title:	IMPLEMENTING INTEGRATED CIRCUIT CHIP ATTACH IN THREE DIMENSIONAL STACK USING VAPOR DEPOSITED SOLDER CU PILLARS

Patent #:	9911716	Issue Dt:	03/06/2018	Application #:	14609237	Filing Dt:	01/29/2015
Publication #:	US20160225742	Pub Dt:	08/04/2016
Title:	POLYGON DIE PACKAGING

Patent #:	9391030	Issue Dt:	07/12/2016	Application #:	14625943	Filing Dt:	02/19/2015
Title:	ON-CHIP SEMICONDUCTOR DEVICE HAVING ENHANCED VARIABILITY

Patent #:	9312275	Issue Dt:	04/12/2016	Application #:	14642937	Filing Dt:	03/10/2015
Publication #:	US20150187816	Pub Dt:	07/02/2015
Title:	FINFET WITH REDUCED CAPACITANCE

Patent #:	9899274	Issue Dt:	02/20/2018	Application #:	14658269	Filing Dt:	03/16/2015
Publication #:	US20160276226	Pub Dt:	09/22/2016
Title:	LOW-COST SOI FINFET TECHNOLOGY

Patent #:	9431425	Issue Dt:	08/30/2016	Application #:	14674586	Filing Dt:	03/31/2015
Title:	DIRECTLY FORMING SiGe FINS ON OXIDE

Patent #:	9514929	Issue Dt:	12/06/2016	Application #:	14677704	Filing Dt:	04/02/2015
Publication #:	US20160293407	Pub Dt:	10/06/2016
Title:	DIELECTRIC FILLING MATERIALS WITH IONIC COMPOUNDS

Patent #:	9431235	Issue Dt:	08/30/2016	Application #:	14695705	Filing Dt:	04/24/2015
Title:	MULTILAYER DIELECTRIC STRUCTURES WITH GRADED COMPOSITION FOR NANO-SCALE SEMICONDUCTOR DEVICES

Patent #:	9412654	Issue Dt:	08/09/2016	Application #:	14697056	Filing Dt:	04/27/2015
Title:	GRAPHENE SACRIFICIAL DEPOSITION LAYER ON BEOL COPPER LINER-SEED FOR MITIGATING QUEUE-TIME ISSUES BETWEEN LINER AND PLATING STEP

Patent #:	9299591	Issue Dt:	03/29/2016	Application #:	14698224	Filing Dt:	04/28/2015
Title:	IMPLEMENTING INTEGRATED CIRCUIT CHIP ATTACH IN THREE DIMENSIONAL STACK USING VAPOR DEPOSITED SOLDER CU PILLARS

Patent #:	9514992	Issue Dt:	12/06/2016	Application #:	14706288	Filing Dt:	05/07/2015
Publication #:	US20160329251	Pub Dt:	11/10/2016
Title:	UNIDIRECTIONAL SPACER IN TRENCH SILICIDE

Patent #:	9892910	Issue Dt:	02/13/2018	Application #:	14713099	Filing Dt:	05/15/2015
Publication #:	US20160336176	Pub Dt:	11/17/2016
Title:	METHOD AND STRUCTURE FOR FORMING A DENSE ARRAY OF SINGLE CRYSTALLINE SEMICONDUCTOR NANOCRYSTALS

Patent #:	9293373	Issue Dt:	03/22/2016	Application #:	14721574	Filing Dt:	05/26/2015
Title:	METHOD FOR FABRICATING CMOS FINFETS WITH DUAL CHANNEL MATERIAL

Patent #:	9576979	Issue Dt:	02/21/2017	Application #:	14722237	Filing Dt:	05/27/2015
Publication #:	US20160351590	Pub Dt:	12/01/2016
Title:	PREVENTING STRAINED FIN RELAXATION BY SEALING FIN ENDS

Patent #:	9892935	Issue Dt:	02/13/2018	Application #:	14724097	Filing Dt:	05/28/2015
Publication #:	US20160351467	Pub Dt:	12/01/2016
Title:	LIMITING ELECTRONIC PACKAGE WARPAGE WITH SEMICONDUCTOR CHIP LID AND LID-RING

Patent #:	10340241	Issue Dt:	07/02/2019	Application #:	14736943	Filing Dt:	06/11/2015
Publication #:	US20160365328	Pub Dt:	12/15/2016
Title:	CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE

Patent #:	9627278	Issue Dt:	04/18/2017	Application #:	14741418	Filing Dt:	06/16/2015
Publication #:	US20160372383	Pub Dt:	12/22/2016
Title:	METHOD OF SOURCE/DRAIN HEIGHT CONTROL IN DUAL EPI FINFET FORMATION

Patent #:	9379025	Issue Dt:	06/28/2016	Application #:	14744080	Filing Dt:	06/19/2015
Title:	METHOD OF FORMING SOURCE/DRAIN CONTACTS IN UNMERGED FINFETS

Patent #:	9514987	Issue Dt:	12/06/2016	Application #:	14744681	Filing Dt:	06/19/2015
Publication #:	US20160372372	Pub Dt:	12/22/2016
Title:	BACKSIDE CONTACT TO FINAL SUBSTRATE

Patent #:	9685340	Issue Dt:	06/20/2017	Application #:	14753827	Filing Dt:	06/29/2015
Publication #:	US20160379925	Pub Dt:	12/29/2016
Title:	STABLE CONTACT ON ONE-SIDED GATE TIE-DOWN STRUCTURE

Patent #:	9478427	Issue Dt:	10/25/2016	Application #:	14832019	Filing Dt:	08/21/2015
Publication #:	US20150364416	Pub Dt:	12/17/2015
Title:	SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

Patent #:	9620371	Issue Dt:	04/11/2017	Application #:	14832021	Filing Dt:	08/21/2015
Publication #:	US20150364368	Pub Dt:	12/17/2015
Title:	SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

Patent #:	10438803	Issue Dt:	10/08/2019	Application #:	14832024	Filing Dt:	08/21/2015
Publication #:	US20150364367	Pub Dt:	12/17/2015
Title:	SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

Patent #:	9761482	Issue Dt:	09/12/2017	Application #:	14835256	Filing Dt:	08/25/2015
Publication #:	US20150364365	Pub Dt:	12/17/2015
Title:	ENHANCEMENT OF ISO-VIA RELIABILITY

Patent #:	9997411	Issue Dt:	06/12/2018	Application #:	14837580	Filing Dt:	08/27/2015
Publication #:	US20150364419	Pub Dt:	12/17/2015
Title:	FORMATION OF METAL RESISTOR AND E-FUSE

Patent #:	9934980	Issue Dt:	04/03/2018	Application #:	14838491	Filing Dt:	08/28/2015
Publication #:	US20150371863	Pub Dt:	12/24/2015
Title:	REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING

Patent #:	9472463	Issue Dt:	10/18/2016	Application #:	14839157	Filing Dt:	08/28/2015
Publication #:	US20150371904	Pub Dt:	12/24/2015
Title:	PATTERNING PROCESS FOR FIN IMPLANTATION

Patent #:	9716028	Issue Dt:	07/25/2017	Application #:	14840001	Filing Dt:	08/30/2015
Publication #:	US20150371887	Pub Dt:	12/24/2015
Title:	UNIVERSAL CLAMPING FIXTURE TO MAINTAIN LAMINATE FLATNESS DURING CHIP JOIN

Patent #:	9735041	Issue Dt:	08/15/2017	Application #:	14840004	Filing Dt:	08/30/2015
Publication #:	US20150371888	Pub Dt:	12/24/2015
Title:	UNIVERSAL CLAMPING FIXTURE TO MAINTAIN LAMINATE FLATNESS DURING CHIP JOIN

Patent #:	10171629	Issue Dt:	01/01/2019	Application #:	14847051	Filing Dt:	09/08/2015
Publication #:	US20170070597	Pub Dt:	03/09/2017
Title:	CLIENT-INITIATED LEADER ELECTION IN DISTRIBUTED CLIENT-SERVER SYSTEMS

Patent #:	9449810	Issue Dt:	09/20/2016	Application #:	14847350	Filing Dt:	09/08/2015
Publication #:	US20160005597	Pub Dt:	01/07/2016
Title:	ADVANCED ULTRA LOW K SICOH DIELECTRICS PREPARED BY BUILT-IN ENGINEERED PORE SIZE AND BONDING STRUCTURED WITH CYCLIC ORGANOSILICON PRECURSORS

Patent #:	9496148	Issue Dt:	11/15/2016	Application #:	14850491	Filing Dt:	09/10/2015
Title:	METHOD OF CHARGE CONTROLLED PATTERNING DURING REACTIVE ION ETCHING

Patent #:	9397152	Issue Dt:	07/19/2016	Application #:	14851345	Filing Dt:	09/11/2015
Publication #:	US20160126305	Pub Dt:	05/05/2016
Title:	MULTILAYER MIM CAPACITOR

Patent #:	9484239	Issue Dt:	11/01/2016	Application #:	14858014	Filing Dt:	09/18/2015
Publication #:	US20160079111	Pub Dt:	03/17/2016
Title:	Sacrificial Carrier Dicing of Semiconductor Wafers

Patent #:	9425079	Issue Dt:	08/23/2016	Application #:	14864080	Filing Dt:	09/24/2015
Publication #:	US20160013093	Pub Dt:	01/14/2016
Title:	SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

Patent #:	9698159	Issue Dt:	07/04/2017	Application #:	14864091	Filing Dt:	09/24/2015
Publication #:	US20160013181	Pub Dt:	01/14/2016
Title:	SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

Patent #:	9997408	Issue Dt:	06/12/2018	Application #:	14872302	Filing Dt:	10/01/2015
Publication #:	US20170098577	Pub Dt:	04/06/2017
Title:	METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY

Patent #:	9373538	Issue Dt:	06/21/2016	Application #:	14873824	Filing Dt:	10/02/2015
Publication #:	US20160027687	Pub Dt:	01/28/2016
Title:	INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES

Patent #:	9673064	Issue Dt:	06/06/2017	Application #:	14874393	Filing Dt:	10/03/2015
Publication #:	US20160172290	Pub Dt:	06/16/2016
Title:	INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES

Patent #:	9431340	Issue Dt:	08/30/2016	Application #:	14876009	Filing Dt:	10/06/2015
Publication #:	US20160163642	Pub Dt:	06/09/2016
Title:	WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION

Patent #:	10020306	Issue Dt:	07/10/2018	Application #:	14880658	Filing Dt:	10/12/2015
Publication #:	US20170103984	Pub Dt:	04/13/2017
Title:	SPACER FOR TRENCH EPITAXIAL STRUCTURES

Patent #:	10037895	Issue Dt:	07/31/2018	Application #:	14882548	Filing Dt:	10/14/2015
Publication #:	US20160035716	Pub Dt:	02/04/2016
Title:	STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Patent #:	10283374	Issue Dt:	05/07/2019	Application #:	14882549	Filing Dt:	10/14/2015
Publication #:	US20160035717	Pub Dt:	02/04/2016
Title:	STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Patent #:	9680015	Issue Dt:	06/13/2017	Application #:	14882618	Filing Dt:	10/14/2015
Publication #:	US20160148931	Pub Dt:	05/26/2016
Title:	DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH

Patent #:	9576961	Issue Dt:	02/21/2017	Application #:	14882968	Filing Dt:	10/14/2015
Publication #:	US20160099322	Pub Dt:	04/07/2016
Title:	SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Patent #:	9941191	Issue Dt:	04/10/2018	Application #:	14884076	Filing Dt:	10/15/2015
Publication #:	US20160035650	Pub Dt:	02/04/2016
Title:	NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY

Patent #:	9879152	Issue Dt:	01/30/2018	Application #:	14919070	Filing Dt:	10/21/2015
Publication #:	US20170114246	Pub Dt:	04/27/2017
Title:	BLOCK COPOLYMERS FOR DIRECTED SELF-ASSEMBLY APPLICATIONS

Patent #:	9406617	Issue Dt:	08/02/2016	Application #:	14945754	Filing Dt:	11/19/2015
Title:	STRUCTURE AND PROCESS FOR W CONTACTS

Patent #:	9330946	Issue Dt:	05/03/2016	Application #:	14946904	Filing Dt:	11/20/2015
Title:	METHOD AND STRUCTURE OF DIE STACKING USING PRE-APPLIED UNDERFILL

Patent #:	9721812	Issue Dt:	08/01/2017	Application #:	14947855	Filing Dt:	11/20/2015
Publication #:	US20170148646	Pub Dt:	05/25/2017
Title:	OPTICAL DEVICE WITH PRECOATED UNDERFILL

Patent #:	9559013	Issue Dt:	01/31/2017	Application #:	14948441	Filing Dt:	11/23/2015
Title:	STACKED NANOWIRE SEMICONDUCTOR DEVICE

Patent #:	9466672	Issue Dt:	10/11/2016	Application #:	14951908	Filing Dt:	11/25/2015
Title:	REDUCED DEFECT DENSITIES IN GRADED BUFFER LAYERS BY TENSILE STRAINED INTERLAYERS

Patent #:	9620360	Issue Dt:	04/11/2017	Application #:	14953117	Filing Dt:	11/27/2015
Title:	FABRICATION OF SEMICONDUCTOR JUNCTIONS

Patent #:	10297448	Issue Dt:	05/21/2019	Application #:	14954581	Filing Dt:	11/30/2015
Publication #:	US20170154788	Pub Dt:	06/01/2017
Title:	SiGe FINS FORMED ON A SUBSTRATE

Patent #:	9397006	Issue Dt:	07/19/2016	Application #:	14959407	Filing Dt:	12/04/2015
Title:	CO-INTEGRATION OF DIFFERENT FIN PITCHES FOR LOGIC AND ANALOG DEVICES

Patent #:	9520500	Issue Dt:	12/13/2016	Application #:	14961372	Filing Dt:	12/07/2015
Title:	SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE

Patent #:	9536979	Issue Dt:	01/03/2017	Application #:	14963277	Filing Dt:	12/09/2015
Publication #:	US20160093727	Pub Dt:	03/31/2016
Title:	FINFET WITH REDUCED CAPACITANCE

Patent #:	9570297	Issue Dt:	02/14/2017	Application #:	14963283	Filing Dt:	12/09/2015
Title:	ELIMINATION OF DEFECTS IN LONG ASPECT RATIO TRAPPING TRENCH STRUCTURES

Patent #:	10049896	Issue Dt:	08/14/2018	Application #:	14964256	Filing Dt:	12/09/2015
Publication #:	US20170170030	Pub Dt:	06/15/2017
Title:	LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

Patent #:	9899378	Issue Dt:	02/20/2018	Application #:	14967441	Filing Dt:	12/14/2015
Publication #:	US20170170172	Pub Dt:	06/15/2017
Title:	SIMULTANEOUSLY FABRICATING A HIGH VOLTAGE TRANSISTOR AND A FINFET

Patent #:	9673108	Issue Dt:	06/06/2017	Application #:	14967914	Filing Dt:	12/14/2015
Publication #:	US20170170077	Pub Dt:	06/15/2017
Title:	FABRICATION OF HIGHER-K DIELECTRICS

Patent #:	9537011	Issue Dt:	01/03/2017	Application #:	14968816	Filing Dt:	12/14/2015
Title:	PARTIALLY DIELECTRIC ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET)

Patent #:	9691655	Issue Dt:	06/27/2017	Application #:	14969580	Filing Dt:	12/15/2015
Publication #:	US20170170060	Pub Dt:	06/15/2017
Title:	ETCH STOP IN A DEP-ETCH-DEP PROCESS

Patent #:	10249529	Issue Dt:	04/02/2019	Application #:	14969670	Filing Dt:	12/15/2015
Publication #:	US20170170178	Pub Dt:	06/15/2017
Title:	NOVEL CHANNEL SILICON GERMANIUM FORMATION METHOD

Patent #:	9761455	Issue Dt:	09/12/2017	Application #:	14969708	Filing Dt:	12/15/2015
Publication #:	US20170170019	Pub Dt:	06/15/2017
Title:	MATERIAL REMOVAL PROCESS FOR SELF-ALIGNED CONTACTS

Patent #:	9905463	Issue Dt:	02/27/2018	Application #:	14970120	Filing Dt:	12/15/2015
Publication #:	US20170170068	Pub Dt:	06/15/2017
Title:	SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME

Patent #:	9881896	Issue Dt:	01/30/2018	Application #:	14972164	Filing Dt:	12/17/2015
Publication #:	US20170179077	Pub Dt:	06/22/2017
Title:	ADVANCED CHIP TO WAFER STACKING

Patent #:	9472447	Issue Dt:	10/18/2016	Application #:	14972228	Filing Dt:	12/17/2015
Title:	CONFINED EPTAXIAL GROWTH FOR CONTINUED PITCH SCALING

Patent #:	9640492	Issue Dt:	05/02/2017	Application #:	14973130	Filing Dt:	12/17/2015
Title:	LAMINATE WARPAGE CONTROL

Patent #:	10170337	Issue Dt:	01/01/2019	Application #:	14994598	Filing Dt:	01/13/2016
Publication #:	US20170200620	Pub Dt:	07/13/2017
Title:	IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS

Patent #:	9818746	Issue Dt:	11/14/2017	Application #:	14994650	Filing Dt:	01/13/2016
Publication #:	US20170200719	Pub Dt:	07/13/2017
Title:	STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE

Patent #:	10079182	Issue Dt:	09/18/2018	Application #:	14996575	Filing Dt:	01/15/2016
Publication #:	US20170207132	Pub Dt:	07/20/2017
Title:	FIELD EFFECT TRANSISTOR GATE STACK

Patent #:	9673104	Issue Dt:	06/06/2017	Application #:	15040346	Filing Dt:	02/10/2016
Title:	FABRICATION OF A CMOS STRUCTURE

Patent #:	9502245	Issue Dt:	11/22/2016	Application #:	15042211	Filing Dt:	02/12/2016
Title:	ELIMINATION OF DEFECTS IN LONG ASPECT RATIO TRAPPING TRENCH STRUCTURES

Patent #:	9607898	Issue Dt:	03/28/2017	Application #:	15044169	Filing Dt:	02/16/2016
Title:	SIMULTANEOUSLY FABRICATING A HIGH VOLTAGE TRANSISTOR AND A FINFET

Patent #:	9478425	Issue Dt:	10/25/2016	Application #:	15045474	Filing Dt:	02/17/2016
Title:	FABRICATION OF HIGHER-K DIELECTRICS

Patent #:	9947763	Issue Dt:	04/17/2018	Application #:	15076711	Filing Dt:	03/22/2016
Publication #:	US20160204225	Pub Dt:	07/14/2016
Title:	FINFET WITH REDUCED CAPACITANCE

Patent #:	9941385	Issue Dt:	04/10/2018	Application #:	15077948	Filing Dt:	03/23/2016
Publication #:	US20160204132	Pub Dt:	07/14/2016
Title:	FINFET WITH REDUCED CAPACITANCE

Patent #:	9691718	Issue Dt:	06/27/2017	Application #:	15080650	Filing Dt:	03/25/2016
Publication #:	US20160247770	Pub Dt:	08/25/2016
Title:	ON-CHIP SEMICONDUCTOR DEVICE HAVING ENHANCED VARIABILITY

Patent #:	9768059	Issue Dt:	09/19/2017	Application #:	15092693	Filing Dt:	04/07/2016
Publication #:	US20170294341	Pub Dt:	10/12/2017
Title:	HIGH-CHI BLOCK COPOLYMERS FOR INTERCONNECT STRUCTURES BY DIRECTED SELF-ASSEMBLY

Patent #:	10153158	Issue Dt:	12/11/2018	Application #:	15102553	Filing Dt:	06/08/2016
Publication #:	US20160351391	Pub Dt:	12/01/2016
Title:	SEMICONDUCTOR NANOWIRE FABRICATION

Patent #:	9536780	Issue Dt:	01/03/2017	Application #:	15130814	Filing Dt:	04/15/2016
Title:	METHOD AND APPARATUS FOR SINGLE CHAMBER TREATMENT

Patent #:	9525725	Issue Dt:	12/20/2016	Application #:	15132394	Filing Dt:	04/19/2016
Title:	CLIENT-INITIATED LEADER ELECTION IN DISTRIBUTED CLIENT-SERVER SYSTEMS

Patent #:	9786547	Issue Dt:	10/10/2017	Application #:	15134898	Filing Dt:	04/21/2016
Publication #:	US20170170055	Pub Dt:	06/15/2017
Title:	NOVEL CHANNEL SILICON GERMANIUM FORMATION METHOD

Patent #:	9659817	Issue Dt:	05/23/2017	Application #:	15134959	Filing Dt:	04/21/2016
Publication #:	US20170148675	Pub Dt:	05/25/2017
Title:	STRUCTURE AND PROCESS FOR W CONTACTS

Patent #:	9653403	Issue Dt:	05/16/2017	Application #:	15134975	Filing Dt:	04/21/2016
Publication #:	US20170148736	Pub Dt:	05/25/2017
Title:	STRUCTURE AND PROCESS FOR W CONTACTS

Patent #:	9934963	Issue Dt:	04/03/2018	Application #:	15152777	Filing Dt:	05/12/2016
Publication #:	US20160314965	Pub Dt:	10/27/2016
Title:	MULTILAYER DIELECTRIC STRUCTURES WITH GRADED COMPOSITION FOR NANO-SCALE SEMICONDUCTOR DEVICES

Patent #:	9997419	Issue Dt:	06/12/2018	Application #:	15158685	Filing Dt:	05/19/2016
Publication #:	US20170178976	Pub Dt:	06/22/2017
Title:	CONFINED EPTAXIAL GROWTH FOR CONTINUED PITCH SCALING

Patent #:	10319633	Issue Dt:	06/11/2019	Application #:	15164063	Filing Dt:	05/25/2016
Publication #:	US20160276217	Pub Dt:	09/22/2016
Title:	DIFFUSION BARRIER LAYER FORMATION

Patent #:	9847251	Issue Dt:	12/19/2017	Application #:	15164071	Filing Dt:	05/25/2016
Publication #:	US20160268161	Pub Dt:	09/15/2016
Title:	DIFFUSION BARRIER LAYER FORMATION

Patent #:	9735010	Issue Dt:	08/15/2017	Application #:	15166645	Filing Dt:	05/27/2016
Title:	FABRICATION OF SEMICONDUCTOR FIN STRUCTURES

Patent #:	10249492	Issue Dt:	04/02/2019	Application #:	15166825	Filing Dt:	05/27/2016
Publication #:	US20170345654	Pub Dt:	11/30/2017
Title:	FABRICATION OF COMPOUND SEMICONDUCTOR STRUCTURES

Patent #:	9666489	Issue Dt:	05/30/2017	Application #:	15168367	Filing Dt:	05/31/2016
Publication #:	US20170148683	Pub Dt:	05/25/2017
Title:	STACKED NANOWIRE SEMICONDUCTOR DEVICE

Patent #:	9691623	Issue Dt:	06/27/2017	Application #:	15178893	Filing Dt:	06/10/2016
Publication #:	US20160284645	Pub Dt:	09/29/2016
Title:	SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

Patent #:	9659961	Issue Dt:	05/23/2017	Application #:	15196681	Filing Dt:	06/29/2016
Publication #:	US20160307918	Pub Dt:	10/20/2016
Title:	SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

Patent #:	9768195	Issue Dt:	09/19/2017	Application #:	15196735	Filing Dt:	06/29/2016
Publication #:	US20160307806	Pub Dt:	10/20/2016
Title:	SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

100

Patent #:	9997367	Issue Dt:	06/12/2018	Application #:	15212972	Filing Dt:	07/18/2016
Publication #:	US20160329214	Pub Dt:	11/10/2016
Title:	NON-LITHOGRAPHIC LINE PATTERN FORMATION

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

03/06/2020

Assignee

ELPIS TECHNOLOGIES INC.

1891 ROBERTSON ROAD

SUITE 100

OTTAWA, CANADA K2H 5B7

Correspondence name and address
	ELPIS TECHNOLOGIES INC.
	1891 ROBERTSON ROAD
	SUITE 100
	OTTAWA, K2H 5B7 CANADA

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