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Patent Assignment Details
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Reel/Frame:052561/0161   Pages: 20
Recorded: 05/04/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 316
Page 4 of 4
Pages: 1 2 3 4
1
Patent #:
Issue Dt:
03/19/2019
Application #:
15991003
Filing Dt:
05/29/2018
Publication #:
Pub Dt:
11/15/2018
Title:
POROUS TIN OXIDE FILMS
2
Patent #:
Issue Dt:
04/02/2019
Application #:
16016454
Filing Dt:
06/22/2018
Title:
TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP
3
Patent #:
Issue Dt:
03/19/2019
Application #:
16016477
Filing Dt:
06/22/2018
Title:
TUNNEL TRANSISTOR
4
Patent #:
Issue Dt:
11/05/2019
Application #:
16023533
Filing Dt:
06/29/2018
Publication #:
Pub Dt:
10/25/2018
Title:
PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE
5
Patent #:
Issue Dt:
06/04/2019
Application #:
16045788
Filing Dt:
07/26/2018
Publication #:
Pub Dt:
05/09/2019
Title:
TONE INVERSION INTEGRATION FOR PHASE CHANGE MEMORY
6
Patent #:
Issue Dt:
07/09/2019
Application #:
16159673
Filing Dt:
10/14/2018
Publication #:
Pub Dt:
05/09/2019
Title:
TRANSISTOR WITH ASYMMETRIC SPACERS
7
Patent #:
Issue Dt:
01/21/2020
Application #:
16162535
Filing Dt:
10/17/2018
Publication #:
Pub Dt:
05/30/2019
Title:
SOURCE AND DRAIN FORMATION USING SELF-ALIGNED PROCESSES
8
Patent #:
Issue Dt:
07/09/2019
Application #:
16207274
Filing Dt:
12/03/2018
Publication #:
Pub Dt:
04/18/2019
Title:
CLIENT-INITIATED LEADER ELECTION IN DISTRIBUTED CLIENT-SERVER SYSTEMS
9
Patent #:
Issue Dt:
02/18/2020
Application #:
16238142
Filing Dt:
01/02/2019
Publication #:
Pub Dt:
07/11/2019
Title:
LOCAL WIRING IN BETWEEN STACKED DEVICES
10
Patent #:
Issue Dt:
02/18/2020
Application #:
16245979
Filing Dt:
01/11/2019
Publication #:
Pub Dt:
05/30/2019
Title:
MICROSTRUCTURE MODULATION FOR METAL WAFER-WAFER BONDING
11
Patent #:
Issue Dt:
11/19/2019
Application #:
16278693
Filing Dt:
02/18/2019
Title:
TUNNEL TRANSISTOR
12
Patent #:
Issue Dt:
12/17/2019
Application #:
16291367
Filing Dt:
03/04/2019
Publication #:
Pub Dt:
12/26/2019
Title:
TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP
13
Patent #:
Issue Dt:
02/11/2020
Application #:
16353332
Filing Dt:
03/14/2019
Publication #:
Pub Dt:
07/11/2019
Title:
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
14
Patent #:
Issue Dt:
01/07/2020
Application #:
16371030
Filing Dt:
03/31/2019
Publication #:
Pub Dt:
07/25/2019
Title:
FABRICATION OF COMPOUND SEMICONDUCTOR STRUCTURES
15
Patent #:
Issue Dt:
01/14/2020
Application #:
16391990
Filing Dt:
04/23/2019
Publication #:
Pub Dt:
08/15/2019
Title:
METHODS AND STRUCTURES FOR FORMING UNIFORM FINS WHEN USING HARDMASK PATTERNS
16
Patent #:
Issue Dt:
12/24/2019
Application #:
16504244
Filing Dt:
07/06/2019
Publication #:
Pub Dt:
10/31/2019
Title:
TRANSISTOR WITH ASYMMETRIC SPACERS
Assignor
1
Exec Dt:
03/06/2020
Assignee
1
1891 ROBERTSON ROAD
SUITE 100
OTTAWA, CANADA K2H 5B7
Correspondence name and address
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD
SUITE 100
OTTAWA, K2H 5B7 CANADA

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