Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 051132/0172 | |
| Pages: | 6 |
| | Recorded: | 11/27/2019 | | |
| Conveyance: | RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10444219
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Filing Dt:
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05/23/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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LAMINATION AND DELAMINATION TECHNIQUE FOR THIN FILM PROCESSING
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10444435
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Filing Dt:
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05/23/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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LAMINATION AND DELAMINATION TECHNIQUE FOR THIN FILM PROCESSING
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11034634
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Filing Dt:
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01/13/2005
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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THIN FILM NON VOLATILE MEMORY DEVICE SCALABLE TO SMALL SIZES
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11034637
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Filing Dt:
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01/13/2005
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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METHOD TO FABRICATE A THIN FILM NON VOLATILE MEMORY DEVICE SCALABLE TO SMALL SIZES
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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11206605
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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02/22/2007
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Title:
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METHOD OF PACKAGING AND INTERCONNECTION OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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11206606
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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02/22/2007
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Title:
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METHOD OF PACKAGING AND INTERCONNECTION OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11874907
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
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02/14/2008
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Title:
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METHOD OF PACKAGING AND INTERCONNECTION OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12582940
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Filing Dt:
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10/21/2009
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Publication #:
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Pub Dt:
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02/18/2010
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Title:
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METHOD OF PACKAGING AND INTERCONNECTION OF INTEGRATED CIRCUITS
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Assignee
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| 665 LYTTON AVE., STE. 6 |
| PALO ALTO, CALIFORNIA 94301 |
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Correspondence name and address
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SHARON MASON
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185 ASYLUM STREET
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36TH FLOOR
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HARTFORD, CT 06103
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