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Reel/Frame:040014/0173   Pages: 8
Recorded: 09/13/2016
Attorney Dkt #:VLSIS001-FREESCALE
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE SIGNATURE PAGE PREVIOUSLY RECORDED AT REEL: 039490 FRAME: 0701. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT .
Total properties: 22
1
Patent #:
6147510
Issue Dt:
11/14/2000
Application #:
09114119
Filing Dt:
07/13/1998
Title:
INTEGRATED CIRCUIT FOR HANDLING BUFFER CONTENTION AND METHOD THEREOF
2
Patent #:
6111796
Issue Dt:
08/29/2000
Application #:
09259454
Filing Dt:
03/01/1999
Title:
PROGRAMMABLE DELAY CONTROL IN A MEMORY
3
Patent #:
5978286
Issue Dt:
11/02/1999
Application #:
09259455
Filing Dt:
03/01/1999
Title:
TIMING CONTROL OF AMPLIFIERS IN A MEMORY
4
Patent #:
6274478
Issue Dt:
08/14/2001
Application #:
09352136
Filing Dt:
07/13/1999
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
5
Patent #:
6108266
Issue Dt:
08/22/2000
Application #:
09428440
Filing Dt:
10/28/1999
Title:
MEMORY UTILIZING A PROGRAMMABLE DELAY TO CONTROL ADDRESS BUFFERS
6
Patent #:
6385101
Issue Dt:
05/07/2002
Application #:
09543532
Filing Dt:
04/06/2000
Title:
PROGRAMMABLE DELAY CONTROL FOR SENSE AMPLIFIERS IN A MEMORY
7
Patent #:
6380760
Issue Dt:
04/30/2002
Application #:
09636493
Filing Dt:
08/11/2000
Title:
Integrated circuit for handling buffer contention and method thereof
8
Patent #:
6444569
Issue Dt:
09/03/2002
Application #:
09835276
Filing Dt:
04/16/2001
Publication #:
US20010027083
Pub Dt:
10/04/2001
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
9
Patent #:
6657502
Issue Dt:
12/02/2003
Application #:
09968171
Filing Dt:
10/01/2001
Publication #:
US20030062960
Pub Dt:
04/03/2003
Title:
MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR
10
Patent #:
6573173
Issue Dt:
06/03/2003
Application #:
10175637
Filing Dt:
06/20/2002
Publication #:
US20020151167
Pub Dt:
10/17/2002
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
11
Patent #:
7247552
Issue Dt:
07/24/2007
Application #:
11033009
Filing Dt:
01/11/2005
Publication #:
US20060154470
Pub Dt:
07/13/2006
Title:
INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR
12
Patent #:
7268588
Issue Dt:
09/11/2007
Application #:
11170398
Filing Dt:
06/29/2005
Publication #:
US20070008001
Pub Dt:
01/11/2007
Title:
CASCADABLE LEVEL SHIFTER CELL
13
Patent #:
7709303
Issue Dt:
05/04/2010
Application #:
11328668
Filing Dt:
01/10/2006
Publication #:
US20070161171
Pub Dt:
07/12/2007
Title:
PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE
14
Patent #:
7286423
Issue Dt:
10/23/2007
Application #:
11362694
Filing Dt:
02/27/2006
Publication #:
US20070201298
Pub Dt:
08/30/2007
Title:
BIT LINE PRECHARGE IN EMBEDDED MEMORY
15
Patent #:
7440354
Issue Dt:
10/21/2008
Application #:
11433998
Filing Dt:
05/15/2006
Publication #:
US20070263474
Pub Dt:
11/15/2007
Title:
MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
16
Patent #:
7443745
Issue Dt:
10/28/2008
Application #:
11612626
Filing Dt:
12/19/2006
Publication #:
US20080144409
Pub Dt:
06/19/2008
Title:
BYTE WRITEABLE MEMORY WITH BIT-COLUMN VOLTAGE SELECTION AND COLUMN REDUNDANCY
17
Patent #:
7880516
Issue Dt:
02/01/2011
Application #:
11910062
Filing Dt:
09/28/2007
Publication #:
US20080265958
Pub Dt:
10/30/2008
Title:
METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES
18
Patent #:
NONE
Issue Dt:
02/01/2011
Application #:
11910062
Filing Dt:
09/28/2007
Publication #:
US20080265958
Pub Dt:
10/30/2008
PCT #:
EP0504647
Title:
METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES
19
Patent #:
8020014
Issue Dt:
09/13/2011
Application #:
11914079
Filing Dt:
11/09/2007
Publication #:
US20080209248
Pub Dt:
08/28/2008
Title:
METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES
20
Patent #:
NONE
Issue Dt:
09/13/2011
Application #:
11914079
Filing Dt:
11/09/2007
Publication #:
US20080209248
Pub Dt:
08/28/2008
PCT #:
IB0551539
Title:
METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES
21
Patent #:
7706207
Issue Dt:
04/27/2010
Application #:
12209477
Filing Dt:
09/12/2008
Publication #:
US20090021990
Pub Dt:
01/22/2009
Title:
MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
22
Patent #:
8566836
Issue Dt:
10/22/2013
Application #:
12618311
Filing Dt:
11/13/2009
Publication #:
US20110119672
Pub Dt:
05/19/2011
Title:
Multi-Core System on Chip
Assignor
1
FREESCALE SEMICONDUCTOR, INC.
Exec Dt:
08/16/2016
Assignee
1
VLSI TECHNOLOGY LLC
1209 ORANGE STREET
CORPORATION TRUST CENTER
WILMINGTON, DELAWARE 19801
Correspondence name and address
ERIC SCHEUERLEIN
THE MUELLER LAW OFFICE, P.C.
12707 HIGH BLUFF DRIVE, SUITE 200
SAN DIEGO, CA 92130

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