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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036050/0174   Pages: 153
Recorded: 07/02/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 50
1
Patent #:
Issue Dt:
05/10/2011
Application #:
11152375
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
03/08/2007
Title:
JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
2
Patent #:
Issue Dt:
03/15/2011
Application #:
11167310
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
01/05/2006
Title:
SEMICONDUCTOR DEVICE HAVING A DYNAMICALLY RECONFIGURABLE CIRCUIT CONFIGURATION
3
Patent #:
Issue Dt:
03/22/2011
Application #:
11261176
Filing Dt:
10/28/2005
Publication #:
Pub Dt:
05/04/2006
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
4
Patent #:
Issue Dt:
03/29/2011
Application #:
11408866
Filing Dt:
04/20/2006
Title:
DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE
5
Patent #:
Issue Dt:
05/17/2011
Application #:
11444216
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
12/14/2006
Title:
SEMICONDUCTOR DEVICE HAVING LAMINATED ELECTRONIC CONDUCTOR ON BIT LINE
6
Patent #:
Issue Dt:
03/29/2011
Application #:
11493468
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
01/25/2007
Title:
FABRICATION AND METHOD OF OPERATION OF MULTI-LEVEL MEMORY CELL ON SOI SUBSTRATE
7
Patent #:
Issue Dt:
03/22/2011
Application #:
11512229
Filing Dt:
08/30/2006
Publication #:
Pub Dt:
10/04/2007
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
8
Patent #:
Issue Dt:
03/08/2011
Application #:
11608388
Filing Dt:
12/08/2006
Publication #:
Pub Dt:
06/12/2008
Title:
PREVENTION OF OXIDATION OF CARRIER IONS TO IMPROVE MEMORY RETENTION PROPERTIES OF POLYMER MEMORY CELL
9
Patent #:
Issue Dt:
05/24/2011
Application #:
11612413
Filing Dt:
12/18/2006
Publication #:
Pub Dt:
06/19/2008
Title:
DUAL-BIT MEMORY DEVICE HAVING TRENCH ISOLATION MATERIAL DISPOSED NEAR BIT LINE CONTACT AREAS
10
Patent #:
Issue Dt:
02/22/2011
Application #:
11633800
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHODS OF PROGRAMMING AND ERASING RESISTIVE MEMORY DEVICES
11
Patent #:
Issue Dt:
03/29/2011
Application #:
11633941
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD OF ERASING A RESISTIVE MEMORY DEVICE
12
Patent #:
Issue Dt:
03/15/2011
Application #:
11636064
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
06/21/2007
Title:
SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
13
Patent #:
Issue Dt:
03/29/2011
Application #:
11767620
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
FAULTY DANGLING METAL ROUTE DETECTION
14
Patent #:
Issue Dt:
03/08/2011
Application #:
11821653
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
METHOD OF CONSTRUCTING A STACKED-DIE SEMICONDUCTOR STRUCTURE
15
Patent #:
Issue Dt:
04/05/2011
Application #:
11874001
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
16
Patent #:
Issue Dt:
05/17/2011
Application #:
11889636
Filing Dt:
08/15/2007
Publication #:
Pub Dt:
02/28/2008
Title:
CONTROL CIRCUIT OF POWER SUPPLY UNIT WHICH CONTROLS OUTPUT POWER OF EXTERNAL POWER SUPPLY BASED UPON CURRENT FROM THE EXTERNAL POWER SUPPLY, POWER SUPPLY UNIT AND CONTROL METHOD THEREOF
17
Patent #:
Issue Dt:
05/24/2011
Application #:
11902706
Filing Dt:
09/25/2007
Publication #:
Pub Dt:
04/03/2008
Title:
CONTROL CIRCUIT OF SYNCHRONOUS RECTIFICATION TYPE POWER SUPPLY UNIT, SYNCHRONOUS RECTIFICATION TYPE POWER SUPPLY UNIT AND CONTROL METHOD THEREOF
18
Patent #:
Issue Dt:
03/29/2011
Application #:
11934628
Filing Dt:
11/02/2007
Publication #:
Pub Dt:
05/07/2009
Title:
PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
19
Patent #:
Issue Dt:
05/17/2011
Application #:
11945785
Filing Dt:
11/27/2007
Publication #:
Pub Dt:
05/28/2009
Title:
ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
20
Patent #:
Issue Dt:
04/26/2011
Application #:
11983041
Filing Dt:
11/05/2007
Publication #:
Pub Dt:
05/07/2009
Title:
REDUCTION OF PACKAGE HEIGHT IN A STACKED DIE CONFIGURATION
21
Patent #:
Issue Dt:
03/08/2011
Application #:
11984152
Filing Dt:
11/14/2007
Publication #:
Pub Dt:
05/15/2008
Title:
METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE
22
Patent #:
Issue Dt:
03/08/2011
Application #:
12004919
Filing Dt:
12/21/2007
Publication #:
Pub Dt:
07/03/2008
Title:
SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING THE SAME, AND METHOD OF MANUFACTURING THE SAME
23
Patent #:
Issue Dt:
04/26/2011
Application #:
12012390
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
02/19/2009
Title:
PROGRAM AND ERASE DISABLING CONTROL OF WPCAM BY DOUBLE CONTROLS
24
Patent #:
Issue Dt:
05/24/2011
Application #:
12034316
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
08/20/2009
Title:
DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES
25
Patent #:
Issue Dt:
03/29/2011
Application #:
12055437
Filing Dt:
03/26/2008
Publication #:
Pub Dt:
10/02/2008
Title:
DC-DC CONVERTER, POWER SUPPLY VOLTAGE SUPPLYING METHOD, AND POWER SUPPLY VOLTAGE SUPPLYING SYSTEM
26
Patent #:
Issue Dt:
04/26/2011
Application #:
12098248
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
01/22/2009
Title:
SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME
27
Patent #:
Issue Dt:
05/10/2011
Application #:
12109239
Filing Dt:
04/24/2008
Publication #:
Pub Dt:
12/25/2008
Title:
NONVOLATILE STORAGE DEVICE AND BIAS CONTROL METHOD THEREOF
28
Patent #:
Issue Dt:
05/03/2011
Application #:
12136579
Filing Dt:
06/10/2008
Publication #:
Pub Dt:
12/11/2008
Title:
DC-DC CONVERTER AND CONTROL METHOD THEREOF
29
Patent #:
Issue Dt:
04/26/2011
Application #:
12183756
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/05/2009
Title:
SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
30
Patent #:
Issue Dt:
03/08/2011
Application #:
12195307
Filing Dt:
08/20/2008
Publication #:
Pub Dt:
02/26/2009
Title:
PLASMA TREATED METAL SILICIDE LAYER FORMATION
31
Patent #:
Issue Dt:
03/15/2011
Application #:
12234733
Filing Dt:
09/22/2008
Publication #:
Pub Dt:
03/25/2010
Title:
HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
32
Patent #:
Issue Dt:
03/22/2011
Application #:
12235321
Filing Dt:
09/22/2008
Publication #:
Pub Dt:
09/24/2009
Title:
SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION
33
Patent #:
Issue Dt:
03/08/2011
Application #:
12240767
Filing Dt:
09/29/2008
Publication #:
Pub Dt:
10/08/2009
Title:
METHOD FOR DETECTING A VOID
34
Patent #:
Issue Dt:
03/15/2011
Application #:
12246981
Filing Dt:
10/07/2008
Publication #:
Pub Dt:
04/08/2010
Title:
SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
35
Patent #:
Issue Dt:
02/22/2011
Application #:
12253619
Filing Dt:
10/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL STRUCTURE
36
Patent #:
Issue Dt:
05/10/2011
Application #:
12258067
Filing Dt:
10/24/2008
Publication #:
Pub Dt:
10/29/2009
Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
37
Patent #:
Issue Dt:
03/08/2011
Application #:
12336757
Filing Dt:
12/17/2008
Publication #:
Pub Dt:
12/24/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
38
Patent #:
Issue Dt:
03/08/2011
Application #:
12340288
Filing Dt:
12/19/2008
Publication #:
Pub Dt:
06/24/2010
Title:
RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
39
Patent #:
Issue Dt:
05/03/2011
Application #:
12342008
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
06/24/2010
Title:
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
40
Patent #:
Issue Dt:
05/17/2011
Application #:
12342011
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
06/24/2010
Title:
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
41
Patent #:
Issue Dt:
03/29/2011
Application #:
12370932
Filing Dt:
02/13/2009
Publication #:
Pub Dt:
08/19/2010
Title:
PIN DIODE DEVICE AND ARCHITECTURE
42
Patent #:
Issue Dt:
05/10/2011
Application #:
12494104
Filing Dt:
06/29/2009
Publication #:
Pub Dt:
12/30/2010
Title:
MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS
43
Patent #:
Issue Dt:
03/08/2011
Application #:
12508319
Filing Dt:
07/23/2009
Publication #:
Pub Dt:
11/12/2009
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
44
Patent #:
Issue Dt:
03/01/2011
Application #:
12543035
Filing Dt:
08/18/2009
Publication #:
Pub Dt:
12/10/2009
Title:
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE
45
Patent #:
Issue Dt:
03/29/2011
Application #:
12543404
Filing Dt:
08/18/2009
Publication #:
Pub Dt:
01/07/2010
Title:
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
46
Patent #:
Issue Dt:
04/19/2011
Application #:
12574079
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
01/28/2010
Title:
METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
47
Patent #:
Issue Dt:
03/01/2011
Application #:
12574427
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
01/28/2010
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
48
Patent #:
Issue Dt:
03/15/2011
Application #:
12827069
Filing Dt:
06/30/2010
Publication #:
Pub Dt:
10/21/2010
Title:
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
49
Patent #:
Issue Dt:
03/15/2011
Application #:
12891481
Filing Dt:
09/27/2010
Publication #:
Pub Dt:
01/20/2011
Title:
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
50
Patent #:
Issue Dt:
05/17/2011
Application #:
12891532
Filing Dt:
09/27/2010
Publication #:
Pub Dt:
01/20/2011
Title:
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
Assignor
1
Exec Dt:
06/01/2015
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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