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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	015408/0178			Pages:	5
		Recorded:	11/24/2004
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 15

Patent #:	5801715	Issue Dt:	09/01/1998	Application #:	08323580	Filing Dt:	10/17/1994
Title:	MASSIVELY-PARALLEL PROCESSOR ARRAY WITH OUTPUTS FROM INDIVIDUAL PROCESSORS DIRECTLY TO AN EXTERNAL DEVICE WITHOUT INVOLVING OTHER PROCESSORS OR A COMMON PHYSICAL CARRIER

Patent #:	5748872	Issue Dt:	05/05/1998	Application #:	08618397	Filing Dt:	03/19/1996
Title:	DIRECT REPLACEMENT CELL FAULT TOLERANT ARCHITECTURE

Patent #:	6597362	Issue Dt:	07/22/2003	Application #:	09144695	Filing Dt:	09/01/1998
Title:	INTEGRATED CIRCUIT HAVING LITHOGRAPHICAL CELL ARRAY INTERCONNECTIONS

Patent #:	6154855	Issue Dt:	11/28/2000	Application #:	09376194	Filing Dt:	08/18/1999
Title:	EFFICIENT DIRECT REPLACEMENT CELL FAULT TOLERANT ARCHITECTURE

Patent #:	6408402	Issue Dt:	06/18/2002	Application #:	09679168	Filing Dt:	10/04/2000
Title:	Efficient direct replacement cell fault tolerant architecture

Patent #:	6636986	Issue Dt:	10/21/2003	Application #:	10000813	Filing Dt:	11/30/2001
Publication #:	US20020095617	Pub Dt:	07/18/2002
Title:	OUTPUT AND/OR INPUT COORDINATED PROCESSING ARRAY

Patent #:	NONE	Issue Dt:		Application #:	10022851	Filing Dt:	12/20/2001
Publication #:	US20030117183	Pub Dt:	06/26/2003
Title:	Methods, apparatus, and systems for reducing interference on nearby conductors

Patent #:	6703868	Issue Dt:	03/09/2004	Application #:	10022852	Filing Dt:	12/20/2001
Publication #:	US20030117301	Pub Dt:	06/26/2003
Title:	METHODS, APPARATUS, AND SYSTEMS FOR REDUCING INTERFERENCE ON NEARBY CONDUCTORS

Patent #:	7609778	Issue Dt:	10/27/2009	Application #:	10022856	Filing Dt:	12/20/2001
Publication #:	US20030117184	Pub Dt:	06/26/2003
Title:	METHODS, APPARATUS, AND SYSTEMS FOR REDUCING INTERFERENCE ON NEARBY CONDUCTORS

Patent #:	6897497	Issue Dt:	05/24/2005	Application #:	10023478	Filing Dt:	12/20/2001
Publication #:	US20030116827	Pub Dt:	06/26/2003
Title:	METHODS, APPARATUS, AND SYSTEMS FOR REDUCING INTERFERENCE ON NEARBY CONDUCTORS

Patent #:	6928606	Issue Dt:	08/09/2005	Application #:	10323896	Filing Dt:	12/20/2002
Publication #:	US20030120987	Pub Dt:	06/26/2003
Title:	FAULT TOLERANT SCAN CHAIN FOR A PARALLEL PROCESSING SYSTEM

Patent #:	7546570	Issue Dt:	06/09/2009	Application #:	10324071	Filing Dt:	12/20/2002
Publication #:	US20030140188	Pub Dt:	07/24/2003
Title:	COMMUNICATIONS BUS FOR A PARALLEL PROCESSING SYSTEM

Patent #:	6858356	Issue Dt:	02/22/2005	Application #:	10324110	Filing Dt:	12/20/2002
Publication #:	US20030138705	Pub Dt:	07/24/2003
Title:	METHOD OF GENERATING LARGE SCALE SIGNAL PATHS IN A PARALLEL PROCESSING SYSTEM

Patent #:	7299377	Issue Dt:	11/20/2007	Application #:	10368003	Filing Dt:	02/19/2003
Publication #:	US20040015735	Pub Dt:	01/22/2004
Title:	FAULT TOLERANT CELL ARRAY ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	10458734	Filing Dt:	06/11/2003
Publication #:	US20040255096	Pub Dt:	12/16/2004
Title:	Method for continuous linear production of integrated circuits

Assignor

Exec Dt:

10/14/2004

Assignee

1877 CHEMIN POISSANT SUTTON

QUEBEC, CANADA JOE 2KO

Correspondence name and address
	OGILVY RENAULT
	C. MARC BENOIT
	1981 MCGILL COLLEGE AVENUE, SUITE 1600
	MONTREAL, CANADA H3A2Y-3

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