skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:018865/0179   Pages: 4
Recorded: 02/07/2007
Attorney Dkt #:4591-554
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
10/27/2009
Application #:
11671994
Filing Dt:
02/06/2007
Publication #:
Pub Dt:
08/09/2007
Title:
METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDEING FORMING CONTROL GATE LAYER OVER EACH REGION AND REMOVING A PORTION OF THE TUNNEL INSULATING LAYER ON THE LOW VOLTAGE REGION
Assignors
1
Exec Dt:
01/24/2007
2
Exec Dt:
01/24/2007
3
Exec Dt:
01/24/2007
4
Exec Dt:
01/24/2007
Assignee
1
416 MAETAN-DONG, YEONGTONG-GU, SUWON-SI
GYEONGGI-DO, KOREA, REPUBLIC OF
Correspondence name and address
HOSOON LEE
210 SW MORRISON STREET
SUITE 400
PORTLAND, OR 97204

Search Results as of: 05/28/2024 02:12 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT