Total properties:
16
|
|
Patent #:
|
|
Issue Dt:
|
11/25/1997
|
Application #:
|
08754602
|
Filing Dt:
|
11/20/1996
|
Title:
|
METHOD FOR FORMING BLANKET PLANARIZATION OF THE MULTILEVEL INTERCONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08774753
|
Filing Dt:
|
12/30/1996
|
Title:
|
MANUFACTURING PROCESS OF A SPLIT GATE FLASH MEMORY UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08805391
|
Filing Dt:
|
02/24/1997
|
Title:
|
INTRACHIP POWER DISTRIBUTION PACKAGE AND METHOD FOR SEMICONDUCTORS HAVING A SUPPLY NODE ELECTRICALLY INTERCONNECTED WITH ONE OR MORE INTERMEDIATE NODES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08968981
|
Filing Dt:
|
11/12/1997
|
Title:
|
NEW MULTIPLE CHIP MODULE CONFIGURATION TO SIMPLIFY TESTING PROCESS AND REUSE OF KNOWN-GOOD CHIP-SIZE PACKAGE (CSP)
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09048832
|
Filing Dt:
|
03/20/1998
|
Title:
|
COVERED SLIT ISOLATION BETWEEN INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09159079
|
Filing Dt:
|
09/22/1998
|
Title:
|
CONTACT PRESSURE JIG FOR SIGNAL ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09190660
|
Filing Dt:
|
11/12/1998
|
Title:
|
MULTI-CHIP MEMORY APPARATUS AND ASSOCIATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09229139
|
Filing Dt:
|
01/12/1999
|
Publication #:
|
|
Pub Dt:
|
12/06/2001
| | | | |
Title:
|
SOLDER BALLS AND COLUMNS WITH STRATIFIED UNDERFILLS ON SUBSTRATE FOR FLIP CHIP JOINING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09287218
|
Filing Dt:
|
04/05/1999
|
Title:
|
DIRECT-CHIP-ATTACH (DCA) MULTIPLE CHIP MODULE (MCM) WITH REPAIR-CHIP READY SITE T0 SIMPLIFY ASSEMBLING AND TESTING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09313562
|
Filing Dt:
|
05/15/1999
|
Title:
|
FACE-TO-FACE (FTF) STACKED ASSEMBLY OF SUBSTRATE-ON-BARE-CHIP (SOBC) MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09314493
|
Filing Dt:
|
05/18/1999
|
Title:
|
SUBSTRATE ON CHIP (SOC) MULTIPLE-CHIP MODULE (MCM) WITH CHIP-SIZE-PACKAGE (CSP) READY CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09444988
|
Filing Dt:
|
11/23/1999
|
Title:
|
SELF-ALIGNED CONTACT FOR TRENCH DMOS TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09687022
|
Filing Dt:
|
10/13/2000
|
Title:
|
Covered slit isolation between integrated circuit devices
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
09727913
|
Filing Dt:
|
11/28/2000
|
Title:
|
PROCESS FLOW AND CONFIGURATION OF MULTIPLE CHIP MODULE(MCM) MANUFACTURED WITH PRE-TESTED KNOWN GOOD SUBSTRATE(KGS)
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09905416
|
Filing Dt:
|
07/13/2001
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR WAFER ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
10004680
|
Filing Dt:
|
12/05/2001
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
Title:
|
APPARATUS AND METHOD FOR PREVENTING A WAFER MAPPING SYSTEM OF AN SMIF SYSTEM FROM BEING POLLUTED BY CORROSIVE GASES REMAINING ON WAFERS
|
|