Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 055502/0185 | |
| Pages: | 3 |
| | Recorded: | 03/05/2021 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09963500
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Filing Dt:
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09/27/2001
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Publication #:
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Pub Dt:
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04/18/2002
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Title:
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A SEMICONDUCTOR INTERGRATED CIRCUIT HAVING SWITCHING TRANSISTORS AND VARACTORS
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10079464
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Filing Dt:
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02/22/2002
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD OF TERMINATING BUS, BUS TERMINATION RESISTOR, AND WIRING SUBSTRATE HAVING TERMINATED BUSES AND METHOD OF ITS MANUFACTURE
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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11166357
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Filing Dt:
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06/24/2005
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Publication #:
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Pub Dt:
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12/28/2006
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Title:
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GAPFILL USING DEPOSITION-ETCH SEQUENCE
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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11440113
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Filing Dt:
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05/25/2006
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Publication #:
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Pub Dt:
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10/12/2006
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Title:
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METHOD OF MANUFACTURING WIRING SUBSTRATE HAVING TERMINATED BUSES
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Assignee
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| 1, KOTARI-YAKEMACHI, NAGAOKAKYO-SHI, |
| KYOTO, JAPAN 617-8520 |
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Correspondence name and address
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CPA GLOBAL LIMITED
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LIBERATION HOUSE
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CASTLE STREET
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ST HELIER, JEI IBL JERSEY
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