Total properties:
11
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Patent #:
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Issue Dt:
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05/14/2019
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Application #:
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14542298
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Filing Dt:
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11/14/2014
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Publication #:
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Pub Dt:
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05/19/2016
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Title:
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METHOD AND APPARATUS FOR PERFORMING A WEIGHTED QUEUE SCHEDULING USING A SET OF FAIRNESS FACTORS
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Patent #:
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Issue Dt:
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10/23/2018
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Application #:
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14542350
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Filing Dt:
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11/14/2014
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Publication #:
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Pub Dt:
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05/19/2016
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Title:
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PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS
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Patent #:
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Issue Dt:
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10/15/2019
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Application #:
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14542393
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Filing Dt:
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11/14/2014
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Publication #:
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Pub Dt:
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05/19/2016
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Title:
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PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS WITH PRIORITY PROPAGATION
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Patent #:
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Issue Dt:
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03/21/2017
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Application #:
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14634446
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Filing Dt:
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02/27/2015
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Publication #:
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Pub Dt:
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08/04/2016
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Title:
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AUTOMATED FLIP-FLOP INSERTIONS IN PHYSICAL DESIGN WITHOUT PERTURBATION OF ROUTING
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Patent #:
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Issue Dt:
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03/21/2017
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Application #:
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14664680
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Filing Dt:
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03/20/2015
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Publication #:
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Pub Dt:
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09/22/2016
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Title:
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REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED BY FLIP-FLOP INSERTIONS
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Patent #:
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Issue Dt:
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02/18/2020
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Application #:
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14671900
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Filing Dt:
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03/27/2015
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Publication #:
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Pub Dt:
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09/29/2016
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Title:
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METHOD AND APPARATUS FOR BYPASS ROUTING OF MULTICAST DATA PACKETS AND AVOIDING REPLICATION TO REDUCE OVERALL SWITCH LATENCY
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Patent #:
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Issue Dt:
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01/17/2017
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Application #:
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14675307
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Filing Dt:
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03/31/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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IDENTIFYING INVERSION ERROR IN LOGIC EQUIVALENCE CHECK
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Patent #:
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Issue Dt:
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05/28/2019
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Application #:
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14675342
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Filing Dt:
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03/31/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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APPROACH FOR CHIP-LEVEL FLOP INSERTION AND VERIFICATION BASED ON LOGIC INTERFACE DEFINITION
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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14675356
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Filing Dt:
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03/31/2015
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Publication #:
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Pub Dt:
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03/09/2017
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Title:
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DETERMINATION OF FLIP-FLOP COUNT IN PHYSICAL DESIGN
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Patent #:
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Issue Dt:
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11/03/2020
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Application #:
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14675403
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Filing Dt:
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03/31/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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APPROACH FOR LOGIC SIGNAL GROUPING AND RTL GENERATION USING XML
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Patent #:
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Issue Dt:
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11/19/2019
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Application #:
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14675450
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Filing Dt:
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03/31/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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METHOD AND APPARATUS FOR USING MULTIPLE LINKED MEMORY LISTS
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