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Patent Assignment Details

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Reel/Frame:	023778/0195			Pages:	5
		Recorded:	01/14/2010
Attorney Dkt #:	TIPI 5.2-008
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 24

Patent #:	5730932	Issue Dt:	03/24/1998	Application #:	08612614	Filing Dt:	03/06/1996
Title:	LEAD-FREE, TIN-BASED MULTI-COMPONENT SOLDER ALLOYS

Patent #:	5770891	Issue Dt:	06/23/1998	Application #:	08718120	Filing Dt:	09/18/1996
Title:	SOCKET FOR SEMI-PERMANENTLY CONNECTING A SOLDER BALL GRID ARRAY DEVICE USING A DENDRITE INTERPOSER

Patent #:	6759597	Issue Dt:	07/06/2004	Application #:	09017338	Filing Dt:	02/02/1998
Title:	WIRE BONDING TO DUAL METAL COVERED PAD SURFACES

Patent #:	6390439	Issue Dt:	05/21/2002	Application #:	09287370	Filing Dt:	04/07/1999
Title:	HYBRID MOLDS FOR MOLTEN SOLDER SCREENING PROCESS

Patent #:	6583354	Issue Dt:	06/24/2003	Application #:	09300783	Filing Dt:	04/27/1999
Publication #:	US20020046856	Pub Dt:	04/25/2002
Title:	METHOD OF REFORMING REFORMABLE MEMBERS OF AN ELECTRONIC PACKAGE AND THE RESULTANT ELECTRONIC PACKAGE

Patent #:	6341418	Issue Dt:	01/29/2002	Application #:	09301890	Filing Dt:	04/29/1999
Title:	METHOD FOR DIRECT CHIP ATTACH BY SOLDER BUMPS AND AN UNDERFILL LAYER

Patent #:	6774474	Issue Dt:	08/10/2004	Application #:	09438037	Filing Dt:	11/10/1999
Title:	PARTIALLY CAPTURED ORIENTED INTERCONNECTIONS FOR BGA PACKAGES AND A METHOD OF FORMING THE INTERCONNECTIONS

Patent #:	6519845	Issue Dt:	02/18/2003	Application #:	09481478	Filing Dt:	01/11/2000
Title:	WIRE BONDING TO DUAL METAL COVERED PAD SURFACES

Patent #:	6347732	Issue Dt:	02/19/2002	Application #:	09538460	Filing Dt:	03/30/2000
Title:	Circuit board component retention

Patent #:	6518674	Issue Dt:	02/11/2003	Application #:	09805596	Filing Dt:	03/13/2001
Publication #:	US20010008778	Pub Dt:	07/19/2001
Title:	TEMPORARY ATTACH ARTICLE AND METHOD FOR TEMPORARY ATTACH OF DEVICES TO A SUBSTRATE

Patent #:	6762489	Issue Dt:	07/13/2004	Application #:	09989666	Filing Dt:	11/20/2001
Publication #:	US20030094687	Pub Dt:	05/22/2003
Title:	STRUCTURE AND METHOD FOR WIRING TRANSLATION BETWEEN GRIDS WITH NON-INTEGRAL PITCH RATIOS IN CHIP CARRIER MODULES

Patent #:	6847118	Issue Dt:	01/25/2005	Application #:	10001421	Filing Dt:	11/02/2001
Publication #:	US20020036227	Pub Dt:	03/28/2002
Title:	LOW TEMPERATURE SOLDER CHIP ATTACH STRUCTURE

Patent #:	6524888	Issue Dt:	02/25/2003	Application #:	10037536	Filing Dt:	01/04/2002
Publication #:	US20020096746	Pub Dt:	07/25/2002
Title:	METHOD OF ATTACHING A CONFORMAL CHIP CARRIER TO A FLIP CHIP

Patent #:	6566612	Issue Dt:	05/20/2003	Application #:	10055294	Filing Dt:	01/22/2002
Publication #:	US20020062556	Pub Dt:	05/30/2002
Title:	METHOD FOR DIRECT CHIP ATTACH BY SOLDER BUMPS AND AN UNDERFILL LAYER

Patent #:	6978542	Issue Dt:	12/27/2005	Application #:	10402289	Filing Dt:	03/28/2003
Publication #:	US20030196826	Pub Dt:	10/23/2003
Title:	METHOD OF REFORMING REFORMABLE MEMBERS OF AN ELECTRONIC PACKAGE AND THE RESULTANT ELECTRONIC PACKAGE

Patent #:	6995475	Issue Dt:	02/07/2006	Application #:	10666775	Filing Dt:	09/18/2003
Publication #:	US20050062170	Pub Dt:	03/24/2005
Title:	I/C CHIP SUITABLE FOR WIRE BONDING

Patent #:	7070087	Issue Dt:	07/04/2006	Application #:	10707293	Filing Dt:	12/03/2003
Publication #:	US20040214420	Pub Dt:	10/28/2004
Title:	METHOD AND APPARATUS FOR TRANSFERRING SOLDER BUMPS

Patent #:	6995084	Issue Dt:	02/07/2006	Application #:	10708649	Filing Dt:	03/17/2004
Publication #:	US20050208748	Pub Dt:	09/22/2005
Title:	METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING

Patent #:	6994243	Issue Dt:	02/07/2006	Application #:	10974986	Filing Dt:	10/26/2004
Publication #:	US20050109820	Pub Dt:	05/26/2005
Title:	LOW TEMPERATURE SOLDER CHIP ATTACH STRUCTURE AND PROCESS TO PRODUCE A HIGH TEMPERATURE INTERCONNECTION

Patent #:	7473997	Issue Dt:	01/06/2009	Application #:	11162468	Filing Dt:	09/12/2005
Publication #:	US20060009022	Pub Dt:	01/12/2006
Title:	METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING

Patent #:	7014094	Issue Dt:	03/21/2006	Application #:	11221137	Filing Dt:	09/07/2005
Publication #:	US20060005986	Pub Dt:	01/12/2006
Title:	METHOD OF REFORMING REFORMABLE MEMBERS OF AN ELECTRONIC PACKAGE AND THE RESULTANT ELECTRONIC PACKAGE

Patent #:	7572726	Issue Dt:	08/11/2009	Application #:	11271760	Filing Dt:	11/10/2005
Publication #:	US20060081981	Pub Dt:	04/20/2006
Title:	METHOD OF FORMING A BOND PAD ON AN I/C CHIP AND RESULTING STRUCTURE

Patent #:	7767575	Issue Dt:	08/03/2010	Application #:	12348143	Filing Dt:	01/02/2009
Publication #:	US20090163019	Pub Dt:	06/25/2009
Title:	FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING

Assignor

Exec Dt:

12/30/2009

Assignee

3025 ORCHARD PARKWAY

SAN JOSE, CALIFORNIA 95134

Correspondence name and address
	DARYL K. NEFF
	LERNER, DAVID, LITTENBERG, KRUMHOLZ &
	MENTLIK, LLP
	600 SOUTH AVENUE WEST
	WESTFIELD, NJ 07090

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