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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037406/0200   Pages: 12
Recorded: 12/30/2015
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 63
1
Patent #:
Issue Dt:
12/25/1984
Application #:
06403004
Filing Dt:
07/29/1982
Title:
MULTIPLEXER CIRCUITRY FOR HIGH DENSITY ANALOG SIGNALS
2
Patent #:
Issue Dt:
09/11/1990
Application #:
07336017
Filing Dt:
04/10/1989
Title:
MULTIPLEXER CIRCUITRY FOR HIGH DENSITY ANALOG SIGNALS
3
Patent #:
Issue Dt:
06/03/1997
Application #:
08526415
Filing Dt:
09/11/1995
Title:
SENSING AND SELECTING OBSERVED EVENTS FOR SIGNAL PROCESSING
4
Patent #:
Issue Dt:
09/14/1999
Application #:
08777747
Filing Dt:
12/21/1996
Title:
STACKABLE LAYERS CONTAINING ENCAPSULATED IC CHIPS
5
Patent #:
Issue Dt:
02/27/2001
Application #:
09031435
Filing Dt:
02/26/1998
Title:
STACKING LAYERS CONTAINING ENCLOSED IC CHIPS
6
Patent #:
Issue Dt:
02/22/2000
Application #:
09095415
Filing Dt:
06/10/1998
Title:
IC STACK UTILIZING SECONDARY LEADFRAMES
7
Patent #:
Issue Dt:
01/11/2000
Application #:
09095416
Filing Dt:
06/10/1998
Title:
IC STACK UTILIZING BGA CONTACTS
8
Patent #:
Issue Dt:
09/21/1999
Application #:
09166458
Filing Dt:
10/05/1998
Title:
MULTI- ELEMENT MICRO GYRO
9
Patent #:
Issue Dt:
07/18/2000
Application #:
09301847
Filing Dt:
04/29/1999
Title:
MULTI-ELEMENT MICRO GYRO
10
Patent #:
Issue Dt:
06/06/2000
Application #:
09316740
Filing Dt:
05/21/1999
Title:
STACK OF EQUAL LAYER NEO-CHIPS CONTAINING ENCAPSULATED IC CHIPS OF DIFFERENT SIZES
11
Patent #:
Issue Dt:
11/18/2003
Application #:
09427384
Filing Dt:
10/25/1999
Title:
METHOD OF PRDUCING A HIGH QUALITY, HIGH RESOLUTION IMAGE FROM A SEQUENCE OF LOW QUALITY, LOW RESOLUTION IMAGES THAT ARE UNDERSAMPLED AND SUBJECT TO JITTER
12
Patent #:
Issue Dt:
06/17/2003
Application #:
09604782
Filing Dt:
06/26/2000
Title:
MULTI-AXIS MICRO GYRO STRUCTURE
13
Patent #:
Issue Dt:
04/16/2002
Application #:
09812147
Filing Dt:
03/19/2001
Publication #:
Pub Dt:
11/15/2001
Title:
METHOD OF CANCELING QUADRATURE ERROR IN AN ANGULAR RATE SENSOR
14
Patent #:
Issue Dt:
02/04/2003
Application #:
09884880
Filing Dt:
06/19/2001
Publication #:
Pub Dt:
12/19/2002
Title:
MEMS SENSOR WITH SINGLE CENTRAL ANCHOR AND MOTION-LIMITING CONNECTION GEOMETRY
15
Patent #:
Issue Dt:
04/06/2004
Application #:
09893329
Filing Dt:
06/26/2001
Publication #:
Pub Dt:
01/02/2003
Title:
METHOD OF DESIGNING A FLEXURE SYSTEM FOR TUNING THE MODAL RESPONSE OF A DECOUPLED MICROMACHINED GYROSCOPE AND A GYROSCOPED DESIGNED ACCORDING TO THE METHOD
16
Patent #:
Issue Dt:
07/22/2003
Application #:
09921525
Filing Dt:
08/03/2001
Publication #:
Pub Dt:
02/06/2003
Title:
RETRO-REFLECTOR WARM STOP FOR UNCOOLED THERMAL IMAGING CAMERAS AND METHOD OF USING THE SAME
17
Patent #:
Issue Dt:
09/28/2004
Application #:
09938686
Filing Dt:
10/30/2001
Publication #:
Pub Dt:
05/01/2003
Title:
METHOD OF MAKING STACKABLE LAYERS CONTAINING ENCAPSULATED INTEGRATED CIRCUIT CHIPS WITH ONE OR MORE OVERLAYING INTERCONNECT LAYERS
18
Patent #:
Issue Dt:
05/11/2004
Application #:
09948950
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
03/13/2003
Title:
MULTILAYER MODULES WITH FLEXIBLE SUBSTRATES
19
Patent #:
Issue Dt:
05/06/2003
Application #:
09949024
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
03/13/2003
Title:
STACK OF MULTILAYER MODULES WITH HEAT-FOCUSSING METAL LAYER
20
Patent #:
Issue Dt:
04/06/2004
Application #:
09949512
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
03/13/2003
Title:
STACKING OF MULTILAYER MODULES
21
Patent #:
Issue Dt:
12/07/2004
Application #:
09973857
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
10/31/2002
Title:
HIGH SPEED MULTI-STAGE SWITCHING NETWORK FORMED FROM STACKED SWITCHING LAYERS
22
Patent #:
Issue Dt:
05/04/2004
Application #:
10110889
Filing Dt:
08/19/2002
Title:
HIGHLY CONFIGUARABLE CAPACITIVE TRANSDUCER INTERFACE CIRCUIT
23
Patent #:
Issue Dt:
10/19/2004
Application #:
10128728
Filing Dt:
04/22/2002
Publication #:
Pub Dt:
10/23/2003
Title:
METHOD AND APPARATUS FOR CONNECTING VERTICALLY STACKED INTEGRATED CIRCUIT CHIPS
24
Patent #:
Issue Dt:
03/16/2004
Application #:
10142557
Filing Dt:
05/10/2002
Publication #:
Pub Dt:
09/12/2002
Title:
STACKABLE MICROCIRCUIT LAYER FORMED FROM A PLASTIC ENCAPSULATED MICROCIRCUIT AND METHOD OF MAKING THE SAME
25
Patent #:
Issue Dt:
01/13/2015
Application #:
10178390
Filing Dt:
06/24/2002
Publication #:
Pub Dt:
01/09/2003
Title:
Video event capture, storage and processing method and apparatus
26
Patent #:
Issue Dt:
08/31/2004
Application #:
10302680
Filing Dt:
11/21/2002
Publication #:
Pub Dt:
07/10/2003
Title:
STACKABLE LAYERS CONTAINING ENCAPSULATED INTEGRATED CIRCUIT CHIPS WITH ONE OR MORE OVERLYING INTERCONNECT LAYERS AND A METHOD OF MAKING THE SAME
27
Patent #:
Issue Dt:
07/25/2006
Application #:
10346363
Filing Dt:
01/17/2003
Publication #:
Pub Dt:
02/26/2004
Title:
METHOD FOR EFFECTIVELY EMBEDDING VARIOUS INTEGRATED CIRCUITS WITHIN FIELD PROGRAMMABLE GATE ARRAYS
28
Patent #:
Issue Dt:
02/15/2005
Application #:
10347038
Filing Dt:
01/17/2003
Publication #:
Pub Dt:
12/04/2003
Title:
FIELD PROGRAMMABLE GATE ARRAY WITH A VARIABLY WIDE WORD WIDTH MEMORY
29
Patent #:
Issue Dt:
11/22/2005
Application #:
10360244
Filing Dt:
02/07/2003
Publication #:
Pub Dt:
01/08/2004
Title:
STACKABLE LAYERS CONTAINING BALL GRID ARRAY PACKAGES
30
Patent #:
Issue Dt:
10/31/2006
Application #:
10431914
Filing Dt:
05/07/2003
Publication #:
Pub Dt:
03/04/2004
Title:
MULTILAYER MODULES WITH FLEXIBLE SUBSTRATES
31
Patent #:
Issue Dt:
08/26/2008
Application #:
10703177
Filing Dt:
11/06/2003
Publication #:
Pub Dt:
07/29/2004
Title:
NEO-WAFER DEVICE AND METHOD
32
Patent #:
Issue Dt:
07/03/2007
Application #:
10951990
Filing Dt:
09/28/2004
Publication #:
Pub Dt:
02/17/2005
Title:
THREE-DIMENSIONAL MODULE COMPRISED OF LAYERS CONTAINING IC CHIPS WITH OVERLYING INTERCONNECT LAYERS
33
Patent #:
Issue Dt:
10/21/2008
Application #:
10960712
Filing Dt:
10/06/2004
Publication #:
Pub Dt:
03/17/2005
Title:
HIGH SPEED SWITCHING MODULE COMPRISED OF STACKED LAYERS INCORPORATING T-CONNECT STRUCTURES
34
Patent #:
Issue Dt:
01/18/2011
Application #:
10968572
Filing Dt:
10/19/2004
Publication #:
Pub Dt:
04/14/2005
Title:
VERTICALLY STACKED PRE-PACKAGED INTEGRATED CIRCUIT CHIPS
35
Patent #:
Issue Dt:
09/04/2007
Application #:
11037490
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
06/09/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY INCORPORATING DEDICATED MEMORY STACKS
36
Patent #:
Issue Dt:
03/31/2009
Application #:
11062507
Filing Dt:
02/22/2005
Publication #:
Pub Dt:
07/12/2007
Title:
BGA-SCALE STACKS COMPRISED OF LAYERS CONTAINING INTEGRATED CIRCUIT DIE AND A METHOD FOR MAKING THE SAME
37
Patent #:
Issue Dt:
08/31/2010
Application #:
11150712
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
12/15/2005
Title:
STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS
38
Patent #:
Issue Dt:
02/26/2008
Application #:
11197828
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
04/13/2006
Title:
METHOD FOR PRECISION INTEGRATED CIRCUIT DIE SINGULATION USING DIFFERENTIAL ETCH RATES
39
Patent #:
Issue Dt:
07/10/2007
Application #:
11229351
Filing Dt:
09/15/2005
Publication #:
Pub Dt:
03/16/2006
Title:
STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE
40
Patent #:
Issue Dt:
12/06/2011
Application #:
11248659
Filing Dt:
10/11/2005
Publication #:
Pub Dt:
04/27/2006
Title:
ANTI-TAMPER MODULE
41
Patent #:
Issue Dt:
04/03/2007
Application #:
11354370
Filing Dt:
02/14/2006
Publication #:
Pub Dt:
06/22/2006
Title:
METHOD FOR MAKING A NEO-LAYER COMPRISING EMBEDDED DISCRETE COMPONENTS
42
Patent #:
Issue Dt:
04/07/2009
Application #:
11415891
Filing Dt:
05/01/2006
Publication #:
Pub Dt:
03/29/2007
Title:
LOW POWER ELECTRONIC CIRCUIT INCORPORATING REAL TIME CLOCK
43
Patent #:
Issue Dt:
10/26/2010
Application #:
11429468
Filing Dt:
05/05/2006
Publication #:
Pub Dt:
08/19/2010
Title:
GLOBAL POSITIONING USING PLANETARY CONSTANTS
44
Patent #:
Issue Dt:
08/03/2010
Application #:
11441908
Filing Dt:
05/26/2006
Publication #:
Pub Dt:
11/30/2006
Title:
STACKABLE TIER STRUCTURE COMPRISING PREFABRICATED HIGH DENSITY FEEDTHROUGH
45
Patent #:
Issue Dt:
11/02/2010
Application #:
11511117
Filing Dt:
08/26/2006
Publication #:
Pub Dt:
03/01/2007
Title:
MEMS COOLING DEVICE
46
Patent #:
Issue Dt:
04/05/2011
Application #:
11524090
Filing Dt:
09/20/2006
Publication #:
Pub Dt:
02/15/2007
Title:
TIER STRUCTURE WITH TIER FRAME HAVING A FEEDTHROUGH STRUCTURE
47
Patent #:
Issue Dt:
06/03/2008
Application #:
11654292
Filing Dt:
01/16/2007
Title:
ABSOLUTE PRESSURE SENSOR
48
Patent #:
Issue Dt:
10/14/2008
Application #:
11706724
Filing Dt:
02/15/2007
Title:
THREE-DIMENSIONAL LADAR MODULE WITH ALIGNMENT REFERENCE INSERT CIRCUITRY
49
Patent #:
Issue Dt:
08/02/2011
Application #:
11731154
Filing Dt:
03/31/2007
Title:
BALL GRID ARRAY STACK
50
Patent #:
Issue Dt:
07/13/2010
Application #:
11807671
Filing Dt:
05/30/2007
Publication #:
Pub Dt:
02/11/2010
Title:
LARGE FORMAT THERMOELECTRIC INFRARED DETECTOR AND METHOD OF FABRICATION
51
Patent #:
Issue Dt:
01/19/2010
Application #:
11897938
Filing Dt:
08/31/2007
Publication #:
Pub Dt:
03/27/2008
Title:
FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT
52
Patent #:
Issue Dt:
08/10/2010
Application #:
11977447
Filing Dt:
10/24/2007
Title:
WIRE BOND METHOD FOR ANGULARLY DISPOSED CONDUCTIVE PADS AND A DEVICE MADE FROM THE METHOD
53
Patent #:
Issue Dt:
07/16/2013
Application #:
12283746
Filing Dt:
09/15/2008
Title:
CHIP SCALE VACUUM PUMP
54
Patent #:
Issue Dt:
06/12/2012
Application #:
12287691
Filing Dt:
10/10/2008
Publication #:
Pub Dt:
03/26/2009
Title:
THREE-DIMENSIONAL LADAR MODULE WITH ALIGNMENT REFERENCE INSERT CIRCUITRY COMPRISING HIGH DENSITY INTERCONNECT STRUCTURE
55
Patent #:
Issue Dt:
10/18/2011
Application #:
12334383
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
07/02/2009
Title:
FORCED VIBRATION PIEZO GENERATOR AND PIEZO ACTUATOR
56
Patent #:
Issue Dt:
07/24/2012
Application #:
12500434
Filing Dt:
07/09/2009
Title:
STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE
57
Patent #:
Issue Dt:
10/09/2012
Application #:
12607253
Filing Dt:
10/28/2009
Title:
THREE-DIMENSIONAL LADAR MODULE WITH ALIGNMENT REFERENCE INSERT CIRCUITRY
58
Patent #:
Issue Dt:
03/08/2011
Application #:
12639625
Filing Dt:
12/16/2009
Publication #:
Pub Dt:
06/17/2010
Title:
FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT
59
Patent #:
Issue Dt:
10/30/2012
Application #:
12696185
Filing Dt:
01/29/2010
Publication #:
Pub Dt:
06/10/2010
Title:
STACKED BALL GRID ARRAY PACKAGE MODULE UTILIZING ONE OR MORE INTERPOSER LAYERS
60
Patent #:
Issue Dt:
12/25/2012
Application #:
12712810
Filing Dt:
02/25/2010
Title:
METHOD FOR PRECISION INTEGRATED CIRCUIT DIE SINGULATION USING DIFFERENTIAL ETCH RATES
61
Patent #:
Issue Dt:
07/19/2011
Application #:
12731970
Filing Dt:
03/25/2010
Publication #:
Pub Dt:
07/22/2010
Title:
STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE
62
Patent #:
Issue Dt:
09/06/2011
Application #:
12891439
Filing Dt:
09/27/2010
Publication #:
Pub Dt:
02/24/2011
Title:
VERTICALLY STACKED PRE-PACKAGED INTEGRATED CIRCUIT CHIPS
63
Patent #:
Issue Dt:
09/16/2014
Application #:
13181221
Filing Dt:
07/12/2011
Publication #:
Pub Dt:
11/03/2011
Title:
STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE
Assignor
1
Exec Dt:
08/26/2015
Assignee
1
2711 CENTERVILLE RD
SUITE 400
WILMINGTON, DELAWARE 19808
Correspondence name and address
FOLEY & LARDNER LLP
150 EAST GILMAN STREET
VEREX PLAZA
MADISON, WI 53703

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