Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 044100/0200 | |
| Pages: | 36 |
| | Recorded: | 10/02/2017 | | |
| Attorney Dkt #: | TIER PORTFOLIO |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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14949679
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Filing Dt:
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11/23/2015
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Publication #:
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Pub Dt:
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05/12/2016
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15195570
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Filing Dt:
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06/28/2016
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Publication #:
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Pub Dt:
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10/20/2016
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Title:
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PROGRAMMABLE STRUCTURED ARRAYS
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Patent #:
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Issue Dt:
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07/02/2019
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Application #:
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15407242
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Filing Dt:
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01/16/2017
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Publication #:
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Pub Dt:
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05/04/2017
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Title:
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TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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15620142
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Filing Dt:
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06/12/2017
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Publication #:
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Pub Dt:
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09/28/2017
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Title:
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PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
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Assignee
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| 2711 CENTERVILLE RD |
| SUITE 400 |
| WILMINGTON, DELAWARE 19808 |
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Correspondence name and address
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MURABITO HAO & BARNES LLP
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TWO NORTH MARKET STREET
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THIRD FLOOR
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SAN JOSE, CA 95113
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