Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 008328/0204 | |
| Pages: | 6 |
| | Recorded: | 01/31/1997 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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12/26/1995
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Application #:
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08037893
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Filing Dt:
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03/26/1993
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Title:
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FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE
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Patent #:
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Issue Dt:
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02/07/1995
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Application #:
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08038668
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Filing Dt:
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03/26/1993
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Title:
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FLASH MEMORY MASS STORAGE ARCHITECTURE
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Patent #:
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Issue Dt:
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01/16/1996
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Application #:
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08131495
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Filing Dt:
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10/04/1993
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Title:
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FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE WITHOUT USING CAM CELLS
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Patent #:
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Issue Dt:
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02/25/1997
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Application #:
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08326884
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Filing Dt:
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10/21/1994
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Title:
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METHOD AND APPARATUS FOR COMBINING CONTROLLER FIRMWARE STORAGE AND CONTROLLER LOGIC IN A MASS STORAGE SYSTEM
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08420239
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Filing Dt:
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04/11/1995
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Title:
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HIGH PERFORMANCE METHOD OF AND SYSTEM FOR SELECTING ONE OF A PLURALITY OF IC CHIPS WHILE REQUIRING MINIMAL SELECT LINES
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08509706
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Filing Dt:
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07/31/1995
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Title:
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DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08515188
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Filing Dt:
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08/15/1995
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Title:
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A NON-VOLATILE MEMORY SYSTEM OF MULTI-LEVEL TRANSISTOR CELLS AND METHODS USING SAME
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08527484
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Filing Dt:
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09/13/1995
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Title:
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METHOD OF AND ARCHITECTURE FOR CONTROLLING SYSTEM DATA WITH AUTOMATIC WEAR LEVELING IN A SEMICONDUCTOR NON-VOLATILE MASS STORAGE MEMORY
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Assignee
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| 47421 BAYSIDE PARKWAY |
| FREMONT, CALIFORNIA 94538 |
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Correspondence name and address
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LEXAR MICROSYSTEMS, INC.
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MARYAM IMAM
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47421 BAYSIDE PARKWAY
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FREMONT, CALIFORNIA 94538
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