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Reel/Frame:038847/0207   Pages: 4
Recorded: 06/08/2016
Attorney Dkt #:18506-996/US5800
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
06/29/2021
Application #:
15130182
Filing Dt:
04/15/2016
Publication #:
Pub Dt:
10/19/2017
Title:
METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A SEMICONDUCTOR DEVICE LAYER FORMED ON A TEMPORARY SUBSTRATE HAVING A GRADED SIGE ETCH STOP LAYER THERE BETWEEN
Assignors
1
Exec Dt:
05/09/2016
2
Exec Dt:
05/09/2016
3
Exec Dt:
05/09/2016
4
Exec Dt:
06/03/2016
5
Exec Dt:
05/11/2016
6
Exec Dt:
05/11/2016
Assignee
1
NO.8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN
Correspondence name and address
WPAT, PC INTELLECTUAL PROPERTY ATTORNEYS
2301 DUPONT DR. SUITE 510
IRVINE, CA 92612

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