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Reel/Frame:066353/0207   Pages: 27
Recorded: 01/19/2024
Attorney Dkt #:850063.001(OTHER LFS-3)
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 13
1
Patent #:
Issue Dt:
11/06/2007
Application #:
11115538
Filing Dt:
04/27/2005
Publication #:
Pub Dt:
11/23/2006
Title:
ONE-TIME PROGRAMMABLE CIRCUIT EXPLOITING BJT HFE DEGRADATION
2
Patent #:
Issue Dt:
09/02/2008
Application #:
11143916
Filing Dt:
06/01/2005
Publication #:
Pub Dt:
12/22/2005
Title:
LOW-CONSUMPTION INHIBIT CIRCUIT WITH HYSTERESIS
3
Patent #:
Issue Dt:
06/26/2007
Application #:
11159818
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
12/29/2005
Title:
FAST BISTABLE CIRCUIT PROTECTED AGAINST RANDOM EVENTS
4
Patent #:
Issue Dt:
11/27/2007
Application #:
11291478
Filing Dt:
11/30/2005
Publication #:
Pub Dt:
07/13/2006
Title:
ERROR TEST FOR AN ADDRESS DECODER OF A NON-VOLATILE MEMORY
5
Patent #:
Issue Dt:
01/01/2008
Application #:
11400062
Filing Dt:
04/07/2006
Publication #:
Pub Dt:
10/19/2006
Title:
PHASE LOCKED LOOP
6
Patent #:
Issue Dt:
10/02/2007
Application #:
11402286
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
10/26/2006
Title:
GAIN CONTROL FOR CARTESIAN LOOP TRANSMITTER WITH DIGITAL PROCESSING
7
Patent #:
Issue Dt:
01/18/2011
Application #:
11420152
Filing Dt:
05/24/2006
Publication #:
Pub Dt:
11/30/2006
Title:
CAPACITIVE ARRAY
8
Patent #:
Issue Dt:
07/28/2009
Application #:
11913102
Filing Dt:
12/12/2007
Publication #:
Pub Dt:
08/14/2008
Title:
INTEGRATED CIRCUIT HAVING CONFIGURABLE CELLS AND A SECURED TEST MODE
9
Patent #:
Issue Dt:
06/15/2010
Application #:
11960024
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
06/26/2008
Title:
METHOD OF MANUFACTURING SENSOR WITH PHOTODIODE AND CHARGE TRANSFER TRANSISTOR
10
Patent #:
Issue Dt:
04/20/2010
Application #:
11963939
Filing Dt:
12/24/2007
Publication #:
Pub Dt:
06/26/2008
Title:
PINNED PHOTODIODE WITH HIGH STORAGE CAPACITY, METHOD OF MANUFACTURE AND IMAGE SENSOR INCORPORATING SAME
11
Patent #:
Issue Dt:
07/13/2010
Application #:
12333426
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
06/18/2009
Title:
MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT
12
Patent #:
Issue Dt:
06/04/2013
Application #:
12900584
Filing Dt:
10/08/2010
Publication #:
Pub Dt:
04/14/2011
Title:
LOW COMPLEXITY FINITE PRECISION DECODERS AND APPARATUS FOR LDPC CODES
13
Patent #:
Issue Dt:
05/20/2014
Application #:
13312679
Filing Dt:
12/06/2011
Publication #:
Pub Dt:
06/06/2013
Title:
DUAL CLOCK EDGE TRIGGERED MEMORY
Assignor
1
Exec Dt:
01/26/2023
Assignee
1
29 BOULEVARD ROMAIN ROLLAND
MONTROUGE, FRANCE 92120
Correspondence name and address
TESSA MCCLURE
701 FIFTH AVENUE, SUITE 5400
SEED IP LAW GROUP LLP
SEATTLE, WA 98104

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