Total properties:
22
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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07726773
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Filing Dt:
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07/08/1991
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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08/01/1995
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Application #:
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07857599
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Filing Dt:
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03/31/1992
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Title:
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A SYSTEM AND METHOD FOR EXTRACTION, ALIGNMENT AND DECODING OF CISC INSTRUCTIONS INTO A NANO-INSTRUCTION BUCKET FOR EXECUTION BY A RISC COMPUTER
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Patent #:
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Issue Dt:
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03/05/1996
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Application #:
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08219425
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Filing Dt:
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03/29/1994
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Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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08/13/1996
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Application #:
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08440225
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Filing Dt:
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05/12/1995
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Title:
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METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS AND COMBINING THEM INTO A FINAL BUCKET FOR PROCESSING ON A HOST PROCESSOR
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08460272
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Filing Dt:
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06/02/1995
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Title:
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SYSTEM FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS AND COMBINING THEM INTO A FINAL BUCKET FOR PROCESSING ON A HOST PROCESSOR
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08465239
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Filing Dt:
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06/05/1995
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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04/07/1998
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Application #:
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08594401
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Filing Dt:
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01/31/1996
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Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08665845
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Filing Dt:
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06/19/1996
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08784339
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Filing Dt:
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01/16/1997
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Title:
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SUPERSCALAR MICROPROCESSOR FOR OUT-OF-ORDER AND CONCURRENTLY EXECUTING AT LEAST TWO RISC INSTRUCTIONS TRANSLATING FROM IN-ORDER CISC INSTRUCTIONS
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08937361
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Filing Dt:
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09/25/1997
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08990414
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Filing Dt:
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12/15/1997
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Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09188708
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Filing Dt:
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11/10/1998
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09329354
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Filing Dt:
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06/10/1999
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Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09401860
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Filing Dt:
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09/22/1999
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Title:
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SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTION TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09480136
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Filing Dt:
|
01/10/2000
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Title:
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RISC microprocessor architecture implementing multiple typed register sets
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Patent #:
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Issue Dt:
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06/30/2009
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Application #:
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10060086
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10061295
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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05/01/2003
| | | | |
Title:
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SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10086197
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Filing Dt:
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03/01/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11167289
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Filing Dt:
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06/28/2005
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
Title:
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SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
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Patent #:
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Issue Dt:
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03/23/2010
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Application #:
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11651009
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Filing Dt:
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01/09/2007
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
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Patent #:
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|
Issue Dt:
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09/21/2010
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Application #:
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11730566
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Filing Dt:
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04/02/2007
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Publication #:
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Pub Dt:
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03/06/2008
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Title:
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SUPERSCALAR RISC INSTRUCTION SCHEDULING
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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12046318
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Filing Dt:
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03/11/2008
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Publication #:
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Pub Dt:
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07/03/2008
| | | | |
Title:
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SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
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