Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 023319/0219 | |
| Pages: | 2 |
| | Recorded: | 10/02/2009 | | |
| Attorney Dkt #: | 20989US02 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/1998
|
Application #:
|
08624205
|
Filing Dt:
|
04/03/1996
|
|
Title:
|
ARITHMETIC LOGIC UNIT CIRCUIT WITH REDUCED PROPAGATION DELAYS
|
|
|
Assignee
|
|
|
|
|
| 50, HYANGJUNG-DONG, CHEONGJU |
| CHOONGCHUNGBOOK-DO, KOREA, REPUBLIC OF |
|
|
Correspondence name and address
|
| |
MCANDREWS, HELD & MALLOY, LTD.
|
| |
500 W MADISON
|
| |
SUITE 3400
|
| |
CHICAGO, IL 60661
|
Search Results as of:
06/20/2024 09:23 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
