Total properties:
44
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11650238
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Filing Dt:
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01/05/2007
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Publication #:
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Pub Dt:
|
07/10/2008
| | | | |
Title:
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METHODS AND SYSTEMS FOR CONVERTING A SYNCHRONOUS CIRCUIT FABRIC INTO AN ASYNCHRONOUS DATAFLOW CIRCUIT FABRIC
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Patent #:
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Issue Dt:
|
03/17/2009
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Application #:
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11740168
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Filing Dt:
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04/25/2007
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Publication #:
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Pub Dt:
|
11/01/2007
| | | | |
Title:
|
FAULT TOLERANT ASYNCHRONOUS CIRCUITS
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Patent #:
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Issue Dt:
|
03/17/2009
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Application #:
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11740180
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Filing Dt:
|
04/25/2007
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Publication #:
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Pub Dt:
|
11/15/2007
| | | | |
Title:
|
FAULT TOLERANT ASYNCHRONOUS CIRCUITS
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Patent #:
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Issue Dt:
|
10/27/2009
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Application #:
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11740184
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Filing Dt:
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04/25/2007
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Publication #:
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Pub Dt:
|
11/01/2007
| | | | |
Title:
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SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
|
01/24/2012
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Application #:
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12030531
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Filing Dt:
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02/13/2008
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Publication #:
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Pub Dt:
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08/13/2009
| | | | |
Title:
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LOGIC PERFORMANCE IN CYCLIC STRUCTURES
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Patent #:
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Issue Dt:
|
06/15/2010
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Application #:
|
12031992
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Filing Dt:
|
02/15/2008
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Publication #:
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Pub Dt:
|
08/20/2009
| | | | |
Title:
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SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION
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|
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Patent #:
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|
Issue Dt:
|
06/22/2010
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Application #:
|
12240430
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Filing Dt:
|
09/29/2008
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Publication #:
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Pub Dt:
|
01/29/2009
| | | | |
Title:
|
FAULT TOLERANT ASYNCHRONOUS CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
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Application #:
|
12304694
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Filing Dt:
|
05/26/2009
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Publication #:
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|
Pub Dt:
|
01/21/2010
| | | | |
Title:
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RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS
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|
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Patent #:
|
|
Issue Dt:
|
08/23/2011
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Application #:
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12405746
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Filing Dt:
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03/17/2009
|
Publication #:
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|
Pub Dt:
|
11/12/2009
| | | | |
Title:
|
FAULT TOLERANT ASYNCHRONOUS CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
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Application #:
|
12475744
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Filing Dt:
|
06/01/2009
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Publication #:
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Pub Dt:
|
12/02/2010
| | | | |
Title:
|
ASYNCHRONOUS PIPELINED INTERCONNECT ARCHITECTURE WITH FANOUT SUPPORT
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|
|
Patent #:
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|
Issue Dt:
|
04/26/2011
|
Application #:
|
12479299
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Filing Dt:
|
06/05/2009
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
Title:
|
TRANSMISSION FOR AN ELECTRICAL CIRCUIT BREAKER
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|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12505296
|
Filing Dt:
|
07/17/2009
|
Publication #:
|
|
Pub Dt:
|
01/20/2011
| | | | |
Title:
|
NON-PREDICATED TO PREDICATED CONVERSION OF ASYNCHRONOUS REPRESENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12505653
|
Filing Dt:
|
07/20/2009
|
Publication #:
|
|
Pub Dt:
|
01/20/2011
| | | | |
Title:
|
RESET MECHANISM CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12550582
|
Filing Dt:
|
08/31/2009
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
Title:
|
AUTOMATED CONVERSION OF SYNCHRONOUS TO ASYNCHRONOUS CIRCUIT DESIGN REPRESENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12555903
|
Filing Dt:
|
09/09/2009
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
CONVERTING A SYNCHRONOUS CIRCUIT DESIGN INTO AN ASYNCHRONOUS DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12557287
|
Filing Dt:
|
09/10/2009
|
Publication #:
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|
Pub Dt:
|
03/10/2011
| | | | |
Title:
|
PROGRAMMABLE CROSSBAR STRUCTURES IN ASYNCHRONOUS SYSTEMS
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|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12558985
|
Filing Dt:
|
09/14/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
SOURCE-SYNCHRONOUS CLOCKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
12559009
|
Filing Dt:
|
09/14/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
RESET SIGNAL DISTRIBUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12559040
|
Filing Dt:
|
09/14/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
HIERARCHICAL GLOBAL CLOCK TREE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12559069
|
Filing Dt:
|
09/14/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12559102
|
Filing Dt:
|
09/14/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12559573
|
Filing Dt:
|
09/15/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12559612
|
Filing Dt:
|
09/15/2009
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
12570629
|
Filing Dt:
|
09/30/2009
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
ASYCHRONOUS SYSTEM ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12768045
|
Filing Dt:
|
04/27/2010
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
FAULT TOLERANT ASYNCHRONOUS CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12768129
|
Filing Dt:
|
04/27/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
13007933
|
Filing Dt:
|
01/17/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
13022843
|
Filing Dt:
|
02/08/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
13043858
|
Filing Dt:
|
03/09/2011
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
ONE PHASE LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
13310382
|
Filing Dt:
|
12/02/2011
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
RESET SIGNAL DISTRIBUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13350342
|
Filing Dt:
|
01/13/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
ONE PHASE LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13354117
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13427041
|
Filing Dt:
|
03/22/2012
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
RESET MECHANISM CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
14071159
|
Filing Dt:
|
11/04/2013
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
14159869
|
Filing Dt:
|
01/21/2014
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
Title:
|
HIERARCHICAL GLOBAL CLOCK TREE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14629192
|
Filing Dt:
|
02/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
ASYNCHRONOUS PIPELINED INTERCONNECT ARCHITECTURE WITH FANOUT SUPPORT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2020
|
Application #:
|
16134576
|
Filing Dt:
|
09/18/2018
|
Publication #:
|
|
Pub Dt:
|
01/16/2020
| | | | |
Title:
|
EFFICIENT FPGA MULTIPLIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2020
|
Application #:
|
16363434
|
Filing Dt:
|
03/25/2019
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Publication #:
|
|
Pub Dt:
|
10/01/2020
| | | | |
Title:
|
EMBEDDED FPGA TIMING SIGN-OFF
|
|
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Patent #:
|
|
Issue Dt:
|
03/31/2020
|
Application #:
|
16409146
|
Filing Dt:
|
05/10/2019
|
Title:
|
ON-CHIP NETWORK IN PROGRAMMABLE INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2020
|
Application #:
|
16409191
|
Filing Dt:
|
05/10/2019
|
Title:
|
RECONFIGURABLE PROGRAMMABLE INTEGRATED CIRCUIT WITH ON-CHIP NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
16417152
|
Filing Dt:
|
05/20/2019
|
Title:
|
FUSED MEMORY AND ARITHMETIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2022
|
Application #:
|
16535878
|
Filing Dt:
|
08/08/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
Multiple Mode Arithmetic Circuit
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2022
|
Application #:
|
16656685
|
Filing Dt:
|
10/18/2019
|
Publication #:
|
|
Pub Dt:
|
04/22/2021
| | | | |
Title:
|
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2022
|
Application #:
|
16695743
|
Filing Dt:
|
11/26/2019
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Publication #:
|
|
Pub Dt:
|
05/27/2021
| | | | |
Title:
|
NOISE-INDEPENDENT LOSS CHARACTERIZATION OF NETWORKS
|
|