Total properties:
58
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Patent #:
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Issue Dt:
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05/13/1980
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Application #:
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05631729
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Filing Dt:
|
11/13/1975
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Title:
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CMOS STRUCTURE AND METHOD UTILIZING RETARDED ELECTRIC FIELD FOR MINIMUM LATCH-UP
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Patent #:
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Issue Dt:
|
07/17/1979
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Application #:
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05842683
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Filing Dt:
|
10/17/1977
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Title:
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CMOS STRUCTURE AND METHOD UTILIZING RETARDED ELECTRIC FIELD FOR MINIMUM LATCH-UP
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Patent #:
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Issue Dt:
|
05/11/1982
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Application #:
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06018869
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Filing Dt:
|
03/09/1979
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Title:
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CARRIER AND TEST SOCKET FOR LEADLESS INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
06/12/1984
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Application #:
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06248814
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Filing Dt:
|
03/30/1981
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Title:
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HIGH VOLTAGE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
|
12/13/1983
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Application #:
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06371599
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Filing Dt:
|
04/26/1982
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Title:
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METHOD OF FABRICATING MESA MOSFET USING OVERHANG MASK AND RESULTING STRUCTURE
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Patent #:
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Issue Dt:
|
07/28/1987
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Application #:
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06757582
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Filing Dt:
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07/22/1985
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Title:
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METHODS FOR FORMING LATERAL AND VERTICAL DMOS TRANSISTORS
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Patent #:
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Issue Dt:
|
06/16/1987
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Application #:
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06808575
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Filing Dt:
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12/13/1985
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Title:
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POWER SUPPLY HAVING DUAL RAMP CONTROL CIRCUIT
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Patent #:
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Issue Dt:
|
10/18/1988
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Application #:
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06808904
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Filing Dt:
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12/13/1985
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Title:
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INSULATED GATE TRANSISTOR WITH LATCHING INHIBITED
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Patent #:
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Issue Dt:
|
08/23/1988
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Application #:
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06816593
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Filing Dt:
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01/06/1986
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Title:
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INTEGRATED BURIED ZENER DIODE AND TEMPERATURE COMPENSATION TRANSISTOR
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Patent #:
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Issue Dt:
|
01/17/1989
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Application #:
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06838217
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Filing Dt:
|
03/10/1986
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Title:
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METHOD FOR MANUFACTURING A POWER MOS TRANSISTOR
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Patent #:
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Issue Dt:
|
08/30/1988
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Application #:
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06843454
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Filing Dt:
|
03/24/1986
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Title:
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METHOD FOR MAKING PLANAR VERTICAL CHANNEL DMOS STRUCTURES
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Patent #:
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Issue Dt:
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12/29/1987
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Application #:
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06871006
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Filing Dt:
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06/05/1986
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Title:
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FABRICATION OF DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR
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|
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Patent #:
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Issue Dt:
|
11/24/1987
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Application #:
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06894418
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Filing Dt:
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08/08/1986
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Title:
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MANUFACTURE OF TRIMMABLE HIGH VALUE POLYCRYSTALLINE SILICON RESISTOR
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Patent #:
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Issue Dt:
|
05/02/1989
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Application #:
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06927882
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Filing Dt:
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11/06/1986
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Title:
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IMPLANTATION OF IONS INTO AN INSULATING LAYER TO INCREASE PLANAR PN JUNCTION BREAKDOWN VOLTAGE
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|
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Patent #:
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Issue Dt:
|
04/25/1989
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Application #:
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07010924
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Filing Dt:
|
02/05/1987
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Title:
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METHOD FOR OBTAINING REGIONS OF DIELECTRICALLY ISOLATED SINGLE CRYSTAL SILICON
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|
|
Patent #:
|
|
Issue Dt:
|
01/17/1989
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Application #:
|
07014961
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Filing Dt:
|
02/17/1987
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Title:
|
METHOD AND APPARATUS FOR INCREASING BREAKDOWN OF A PLANAR JUNCTION
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|
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Patent #:
|
|
Issue Dt:
|
11/22/1988
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Application #:
|
07019085
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Filing Dt:
|
02/26/1987
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Title:
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METHOD OF FABRICATING A HIGH VOLTAGE SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
08/01/1989
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Application #:
|
07036777
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Filing Dt:
|
04/10/1987
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Title:
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SWITCH INTERFACE CIRCUIT FOR POWER MOSFET GATE DRIVE CONTROL
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Patent #:
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|
Issue Dt:
|
03/07/1989
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Application #:
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07061352
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Filing Dt:
|
06/11/1987
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Title:
|
POWER DMOS TRANSISTOR WITH HIGH SPEED BODY DIODE
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|
|
Patent #:
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|
Issue Dt:
|
06/20/1989
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Application #:
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07074903
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Filing Dt:
|
07/17/1987
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Title:
|
LIMITING SHOOT-THROUGH CURRENT IN A POWER MOSFET HALF-BRIDGE DURING INTRINSIC DIODE RECOVERY
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|
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Patent #:
|
|
Issue Dt:
|
07/26/1988
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Application #:
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07084541
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Filing Dt:
|
08/12/1987
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Title:
|
ION IMPLANTATION OF THIN FILM CRSI2 AND SIC RESISTORS
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|
|
Patent #:
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|
Issue Dt:
|
06/27/1989
|
Application #:
|
07088157
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Filing Dt:
|
08/21/1987
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Title:
|
METHOD OF FABRICATING A HIGH VALUE SEMICONDUCTOR RESISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
09/27/1988
|
Application #:
|
07089184
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Filing Dt:
|
08/25/1987
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Title:
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METHOD OF BONDING SEMICONDUCTOR WAFERS
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|
|
Patent #:
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|
Issue Dt:
|
09/19/1989
|
Application #:
|
07095288
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Filing Dt:
|
09/10/1987
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Title:
|
DOPED SIO2 RESISTOR AND METHOD OF FORMING SAME
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|
|
Patent #:
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|
Issue Dt:
|
12/13/1988
|
Application #:
|
07095481
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Filing Dt:
|
09/10/1987
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Title:
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DENSE VERTICAL J-MOS TRANSISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
05/30/1989
|
Application #:
|
07099452
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Filing Dt:
|
09/21/1987
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Title:
|
DUAL-GATE HIGH DENSITY FET
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|
|
Patent #:
|
|
Issue Dt:
|
11/17/1992
|
Application #:
|
07107725
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Filing Dt:
|
10/08/1987
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Title:
|
VERTICAL CURRENT FLOW FIELD EFFECT TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
07/04/1989
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Application #:
|
07115076
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Filing Dt:
|
10/29/1987
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Title:
|
BURIED GATE JFET
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|
|
Patent #:
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|
Issue Dt:
|
07/25/1989
|
Application #:
|
07120343
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Filing Dt:
|
11/13/1987
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Title:
|
METHOD FOR PROVIDING DIELECTRICALLY ISOLATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
01/09/1990
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Application #:
|
07120395
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Filing Dt:
|
11/13/1987
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Title:
|
METHOD FOR INCREASING THE PERFORMANCE OF TRENCHED DEVICES AND THE RESULTING STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
12/26/1989
|
Application #:
|
07133710
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Filing Dt:
|
12/16/1987
|
Title:
|
HIGH VOLTAGE LEVEL SHIFT SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
03/28/1989
|
Application #:
|
07138989
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Filing Dt:
|
12/29/1987
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Title:
|
A POWER MOS TRANSISTOR WITH EQUIPOTENTIAL RING
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|
|
Patent #:
|
|
Issue Dt:
|
04/03/1990
|
Application #:
|
07138999
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Filing Dt:
|
12/29/1987
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Title:
|
GROOVED DMOS PROCESS WITH VARYING GATE DIELECTRIC THICKNESS
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|
|
Patent #:
|
|
Issue Dt:
|
06/26/1990
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Application #:
|
07141877
|
Filing Dt:
|
01/06/1988
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Title:
|
METHOD FOR IMPROVED ALIGNMENT FOR SEMICONDUCTOR DEVICES WITH BURIED LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/1990
|
Application #:
|
07167617
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Filing Dt:
|
03/14/1988
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Title:
|
TRENCH POWER MOSFET DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
12/27/1988
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Application #:
|
07195436
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Filing Dt:
|
05/16/1988
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Title:
|
HIGH VOLTAGE DRIFTED-DRAIN MOS TRANSISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
08/17/1993
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Application #:
|
07210959
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Filing Dt:
|
06/24/1988
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Title:
|
LIGHTLY DOPED DRAIN MOSFET WITH REDUCED ON-RESISTANCE
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|
|
Patent #:
|
|
Issue Dt:
|
07/23/1991
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Application #:
|
07235842
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Filing Dt:
|
08/24/1988
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Title:
|
PLANAR VERTICAL CHANNEL DMOS STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
01/23/1990
|
Application #:
|
07243166
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Filing Dt:
|
09/08/1988
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Title:
|
VERTICAL DMOS POWER TRANSISTOR WITH AN INTEGRAL OPERATING CONDITION SENSOR
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/1990
|
Application #:
|
07246937
|
Filing Dt:
|
09/19/1988
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Title:
|
POWER TRANSISTOR WITH INTEGRATED GATE RESISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
10/20/1992
|
Application #:
|
07268839
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Filing Dt:
|
11/08/1988
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Title:
|
COMPLEMENTARY, ISOLATED DMOS IC TECHNOLOGY
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|
|
Patent #:
|
|
Issue Dt:
|
10/08/1991
|
Application #:
|
07285842
|
Filing Dt:
|
12/15/1988
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Title:
|
SELF-ALIGNED LDD LATERAL DMOS TRANSISTOR WITH HIGH-VOLTAGE INTERCONNECT CAPABILITY
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|
|
Patent #:
|
|
Issue Dt:
|
12/10/1991
|
Application #:
|
07290546
|
Filing Dt:
|
12/27/1988
|
Title:
|
TRENCH DMOS POWER TRANSISTOR WITH FIELD-SHAPING BODY PROFILE AND THREE-DIMENSIONAL GEOMETRY
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|
|
Patent #:
|
|
Issue Dt:
|
01/08/1991
|
Application #:
|
07292668
|
Filing Dt:
|
12/28/1988
|
Title:
|
VERTICAL DMOS TRANSISTOR FABRICATION PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
01/09/1990
|
Application #:
|
07313737
|
Filing Dt:
|
02/21/1989
|
Title:
|
HIGH VALUE SEMICONDUCTOR RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/1990
|
Application #:
|
07334806
|
Filing Dt:
|
04/05/1989
|
Title:
|
RUGGED LATERAL DMOS TRANSISTOR STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
04/10/1990
|
Application #:
|
07336619
|
Filing Dt:
|
04/07/1989
|
Title:
|
METHOD FOR OBTAINING LOW INTERCONNECT RESISTANCE ON A GROOVED SURFACE AND THE RESULTING STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/1991
|
Application #:
|
07340445
|
Filing Dt:
|
04/19/1989
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Title:
|
HALL SENSING OF BOND WIRE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/1990
|
Application #:
|
07356631
|
Filing Dt:
|
05/22/1989
|
Title:
|
INTEGRATED CIRCUIT WITH HIGH POWER, VERTICAL OUTPUT TRANSISTOR CAPABILITY
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|
|
Patent #:
|
|
Issue Dt:
|
08/28/1990
|
Application #:
|
07406844
|
Filing Dt:
|
09/13/1989
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING THE ON-VOLTAGE CHARACTERISTICS OF A SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
06/05/1990
|
Application #:
|
07420971
|
Filing Dt:
|
10/13/1989
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Title:
|
METHOD OF FABRICATING A SHORT-CHANNEL LOW VOLTAGE DMOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1992
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Application #:
|
07451518
|
Filing Dt:
|
12/15/1989
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Title:
|
MOS TRANSISTOR WITH A CHARGE INDUCED DRAIN EXTENSION
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|
|
Patent #:
|
|
Issue Dt:
|
09/18/1990
|
Application #:
|
07453367
|
Filing Dt:
|
12/21/1989
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Title:
|
JUNCTION FIELD-EFFECT TRANSISTOR WITH A NOVEL GATE
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|
|
Patent #:
|
|
Issue Dt:
|
07/21/1992
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Application #:
|
07498170
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Filing Dt:
|
03/23/1990
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Title:
|
OPTIMIZATION OF BV AND RDS-ON BY GRADED DOPING IN LDD AND OTHER HIGH VOLTAGE IC
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|
|
Patent #:
|
|
Issue Dt:
|
08/04/1992
|
Application #:
|
07597118
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Filing Dt:
|
10/12/1990
|
Title:
|
CLOSED CELL TRANSISTOR WITH BUILT-IN VOLTAGE CLAMP
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Patent #:
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Issue Dt:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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Patent #:
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Issue Dt:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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|
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Patent #:
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Issue Dt:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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