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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	015271/0223			Pages:	3
		Recorded:	10/19/2004
Conveyance:	RELEASE OF SECURITY AGREEMENT

Total properties: 17

Patent #:	6016539	Issue Dt:	01/18/2000	Application #:	08963345	Filing Dt:	11/03/1997
Title:	DATAPATH CONTROL LOGIC FOR PROCESSORS HAVING INSTRUCTION SET ARCHITECTURES IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS

Patent #:	5923894	Issue Dt:	07/13/1999	Application #:	08963346	Filing Dt:	11/03/1997
Title:	ADAPTABLE INPUT/OUTPUT PIN CONTROL

Patent #:	5940626	Issue Dt:	08/17/1999	Application #:	08963387	Filing Dt:	11/03/1997
Title:	PROCESSOR HAVING AN INSTRUCTION SET ARCHITECTURE IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS

Patent #:	6067601	Issue Dt:	05/23/2000	Application #:	08963389	Filing Dt:	11/03/1997
Title:	CACHE MEMORY BASED INSTRUCTION EXECUTION

Patent #:	6178482	Issue Dt:	01/23/2001	Application #:	08963391	Filing Dt:	11/03/1997
Title:	VIRTUAL REGISTER SETS

Patent #:	6216218	Issue Dt:	04/10/2001	Application #:	09120041	Filing Dt:	07/21/1998
Title:	PROCESSOR HAVING A DATAPATH AND CONTROL LOGIC CONSTITUTED WITH BASIS EXECUTION BLOCKS

Patent #:	6438679	Issue Dt:	08/20/2002	Application #:	09120043	Filing Dt:	07/21/1998
Publication #:	US20020053013	Pub Dt:	05/02/2002
Title:	MULTIPLE ISA SUPPORT BY A PROCESSOR USING PRIMITIVE OPERATIONS

Patent #:	6327632	Issue Dt:	12/04/2001	Application #:	09231942	Filing Dt:	01/14/1999
Title:	ADAPTABLE I/O PINS MANIFESTING I/O CHARACTERISTICS RESPONSIVE TO BIT VALUES STORED IN SELECTED ADDRESSABLE STORGE LOCATIONS, EACH PIN COUPLED TO THREE CORRESONDING ADDRESSABLE STORAGE LOCATIONS

Patent #:	6308254	Issue Dt:	10/23/2001	Application #:	09442848	Filing Dt:	11/18/1999
Title:	PROCESSING INSTRUCTIONS OF AN INSTRUCTION SET ARCHITECTURE BY EXECUTING HIERARCHICALLY ORGANIZED SNIPPETS OF ATOMIC UNITS OF PRIMITIVE OPERATIONS

Patent #:	6505291	Issue Dt:	01/07/2003	Application #:	09697911	Filing Dt:	10/26/2000
Title:	PROCESSOR HAVING A DATAPATH AND CONTROL LOGIC CONSTITUTED WITH BASIS EXECUTION BLOCKS

Patent #:	6677786	Issue Dt:	01/13/2004	Application #:	10086500	Filing Dt:	02/28/2002
Publication #:	US20030042506	Pub Dt:	03/06/2003
Title:	MULTI-SERVICE PROCESSOR CLOCKING SYSTEM

Patent #:	7096292	Issue Dt:	08/22/2006	Application #:	10086665	Filing Dt:	02/28/2002
Publication #:	US20020161959	Pub Dt:	10/31/2002
Title:	ON-CHIP INTER-SUBSYSTEM COMMUNICATION

Patent #:	NONE	Issue Dt:		Application #:	10086938	Filing Dt:	02/28/2002
Publication #:	US20020161978	Pub Dt:	10/31/2002
Title:	Multi-service system-on-chip including on-chip memory with multiple access path

Patent #:	7095752	Issue Dt:	08/22/2006	Application #:	10086953	Filing Dt:	02/28/2002
Publication #:	US20020159474	Pub Dt:	10/31/2002
Title:	ON-CHIP INTER-SUBSYSTEM COMMUNICATION INCLUDING CONCURRENT DATA TRAFFIC ROUTING

Patent #:	7107381	Issue Dt:	09/12/2006	Application #:	10301369	Filing Dt:	11/20/2002
Publication #:	US20040098530	Pub Dt:	05/20/2004
Title:	FLEXIBLE DATA TRANSFER TO AND FROM EXTERNAL DEVICE OF SYSTEM-ON-CHIP

Patent #:	7653763	Issue Dt:	01/26/2010	Application #:	10469529	Filing Dt:	08/28/2003
Publication #:	US20040186930	Pub Dt:	09/23/2004
Title:	SUBSYSTEM BOOT AND PERIPHERAL DATA TRANSFER ARCHITECTURE FOR A SUBSYSTEM OF A SYSTEM-ON- CHIP

Assignor

Exec Dt:

03/04/2004

Assignee

44 AIRPORT PARKWAY

SAN JOSE, CALIFORNIA 95110

Correspondence name and address
	PATRICIA A. CONNER
	650 TOWN CENTER DRIVE, SUITE 2000
	COSTA MESA, CA 92626

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