Patent Assignment Details
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| Reel/Frame: | 015247/0227 | |
| Pages: | 3 |
| | Recorded: | 04/21/2004 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10730902
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Filing Dt:
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12/10/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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METHOD OF MAKING SEMICONDUCTOR DEVICE BY POLISHING WITH INTERMEDIATE CLEAN POLISHING
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Assignee
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN |
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Correspondence name and address
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FINNEGAN, HENDERSON, FARABOW, GARRETT &
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LLP - MR. ERNEST F. CHAPMAN
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1300 I STREET, NW
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WASHINGTON, DC 20005
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