Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 007868/0231 | |
| Pages: | 3 |
| | Recorded: | 03/25/1996 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08577895
|
Filing Dt:
|
12/22/1995
|
Title:
|
INTEGRATED CACHE MEMORY WITH SYSTEM CONTROL LOGIC AND ADAPTATION OF RAM BUS TO A CACHE PINOUT
|
|
Assignee
|
|
|
3901 NORTH FIRST STREET |
SAN JOSE, CALIFORNIA 95134 |
|
Correspondence name and address
|
|
BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
|
|
JAMES C. SCHELLER, JR.
|
|
12400 WILSHIRE BLVD.
|
|
7TH FLOOR
|
|
LOS ANGELES, CA 90025
|
Search Results as of:
06/03/2024 11:10 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|