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Reel/Frame:030967/0231   Pages: 5
Recorded: 08/08/2013
Attorney Dkt #:30113-US-PT-10154
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 30
1
Patent #:
6339541
Issue Dt:
01/15/2002
Application #:
09595143
Filing Dt:
06/16/2000
Title:
Architecture for high speed memory circuit having a relatively large number of internal data lines
2
Patent #:
6262935
Issue Dt:
07/17/2001
Application #:
09595149
Filing Dt:
06/17/2000
Title:
Shift redundancy scheme for wordlines in memory circuits
3
Patent #:
6339346
Issue Dt:
01/15/2002
Application #:
09651609
Filing Dt:
08/30/2000
Title:
Low skew signal generation circuit
4
Patent #:
6458644
Issue Dt:
10/01/2002
Application #:
09651938
Filing Dt:
08/31/2000
Title:
DATA BUS ARCHITECTURE FOR INTEGRATED CIRCUIT DEVICES HAVING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH A LARGE ASPECT RATIO PROVIDING REDUCED CAPACITANCE AND POWER REQUIREMENTS
5
Patent #:
6552943
Issue Dt:
04/22/2003
Application #:
09652512
Filing Dt:
08/31/2000
Title:
SENSE AMPLIFIER FOR DYNAMIC RANDOM ACCESS MEMORY ("DRAM") DEVICES HAVING ENHANCED READ AND WRITE SPEED
6
Patent #:
6518829
Issue Dt:
02/11/2003
Application #:
09730207
Filing Dt:
12/04/2000
Publication #:
US20020067201
Pub Dt:
06/06/2002
Title:
DRIVER TIMING AND CIRCUIT TECHNIQUE FOR A LOW NOISE CHARGE PUMP CIRCUIT
7
Patent #:
6566720
Issue Dt:
05/20/2003
Application #:
09794367
Filing Dt:
02/27/2001
Publication #:
US20020040985
Pub Dt:
04/11/2002
Title:
BASE CELL LAYOUT PERMITTING RAPID LAYOUT WITH MINIMUM CLOCK LINE CAPACITANCE ON CMOS STANDARD-CELL AND GATE-ARRAY INTEGRATED CIRCUITS
8
Patent #:
6531900
Issue Dt:
03/11/2003
Application #:
09803315
Filing Dt:
03/09/2001
Publication #:
US20020125918
Pub Dt:
09/12/2002
Title:
NEGATIVE VOLTAGE DRIVER CIRCUIT TECHNIQUE HAVING REDUCED CURRENT FLOW TO THE NEGATIVE SUPPLY VOLTAGE SOURCE
9
Patent #:
6580306
Issue Dt:
06/17/2003
Application #:
09803318
Filing Dt:
03/09/2001
Publication #:
US20020125919
Pub Dt:
09/12/2002
Title:
SWITCHING CIRCUIT UTILIZING A HIGH VOLTAGE TRANSISTOR PROTECTION TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES INCORPORATING DUAL SUPPLY VOLTAGE SOURCES
10
Patent #:
6622198
Issue Dt:
09/16/2003
Application #:
09815148
Filing Dt:
03/22/2001
Publication #:
US20020138685
Pub Dt:
09/26/2002
Title:
LOOK-AHEAD, WRAP-AROUND FIRST-IN, FIRST-OUT INTEGRATED (FIFO) CIRCUIT DEVICE ARCHITECTURE
11
Patent #:
6549470
Issue Dt:
04/15/2003
Application #:
09932331
Filing Dt:
08/17/2001
Publication #:
US20020136051
Pub Dt:
09/26/2002
Title:
SMALL SIGNAL, LOW POWER READ DATA BUS DRIVER FOR INTEGRATED CIRCUIT DEVICES INCORPORATING MEMORY ARRAYS
12
Patent #:
6501817
Issue Dt:
12/31/2002
Application #:
10010336
Filing Dt:
11/13/2001
Publication #:
US20020041198
Pub Dt:
04/11/2002
Title:
AREA EFFICIENT REDUNDANCY MULTIPLEXER CIRCUIT TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES PROVIDING SIGNIFICANTLY REDUCED PARASITIC CAPACITANCE
13
Patent #:
6515926
Issue Dt:
02/04/2003
Application #:
10038932
Filing Dt:
01/04/2002
Title:
SHARED SENSE AMPLIFIER DRIVER TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMORIES EXHIBITING IMPROVED WRITE RECOVERY TIME
14
Patent #:
6512394
Issue Dt:
01/28/2003
Application #:
10098872
Filing Dt:
03/14/2002
Title:
TECHNIQUE FOR EFFICIENT LOGIC POWER GATING WITH DATA RETENTION IN INTEGRATED CIRCUIT DEVICES
15
Patent #:
6643160
Issue Dt:
11/04/2003
Application #:
10230239
Filing Dt:
08/28/2002
Publication #:
US20030022476
Pub Dt:
01/30/2003
Title:
DATA BUS ARCHITECTURE FOR INTEGRATED CIRCUIT DEVICES HAVING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH A LARGE ASPECT RATIO PROVIDING REDUCED CAPACITANCE AND POWER REQUIREMENTS
16
Patent #:
7053692
Issue Dt:
05/30/2006
Application #:
10325524
Filing Dt:
12/19/2002
Publication #:
US20040119529
Pub Dt:
06/24/2004
Title:
POWERGATE CONTROL USING BOOSTED AND NEGATIVE VOLTAGES
17
Patent #:
6788122
Issue Dt:
09/07/2004
Application #:
10354307
Filing Dt:
01/30/2003
Publication #:
US20040150448
Pub Dt:
08/05/2004
Title:
CLOCK CONTROLLED POWER-DOWN STATE
18
Patent #:
6731156
Issue Dt:
05/04/2004
Application #:
10360082
Filing Dt:
02/07/2003
Title:
HIGH VOLTAGE TRANSISTOR PROTECTION TECHNIQUE AND SWITCHING CIRCUIT FOR INTEGRATED CIRCUIT DEVICES UTILIZING MULTIPLE POWER SUPPLY VOLTAGES
19
Patent #:
6738302
Issue Dt:
05/18/2004
Application #:
10360146
Filing Dt:
02/07/2003
Title:
OPTIMIZED READ DATA AMPLIFIER AND METHOD FOR OPERATING THE SAME IN CONJUNCTION WITH INTEGRATED CIRCUIT DEVICES INCORPORATING MEMORY ARRAYS
20
Patent #:
6990029
Issue Dt:
01/24/2006
Application #:
10776054
Filing Dt:
02/11/2004
Publication #:
US20050052917
Pub Dt:
03/10/2005
Title:
COLUMN READ AMPLIFIER POWER-GATING TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY DEVICES AND THOSE DEVICES INCORPORATING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM)
21
Patent #:
7359277
Issue Dt:
04/15/2008
Application #:
10776101
Filing Dt:
02/11/2004
Publication #:
US20050052936
Pub Dt:
03/10/2005
Title:
HIGH SPEED POWER-GATING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES INCORPORATING A SLEEP MODE OF OPERATION
22
Patent #:
7248522
Issue Dt:
07/24/2007
Application #:
10776103
Filing Dt:
02/11/2004
Publication #:
US20050052931
Pub Dt:
03/10/2005
Title:
SENSE AMPLIFIER POWER-GATING TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY DEVICES AND THOSE DEVICES INCORPORATING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM)
23
Patent #:
7110306
Issue Dt:
09/19/2006
Application #:
10878800
Filing Dt:
06/28/2004
Publication #:
US20050286291
Pub Dt:
12/29/2005
Title:
DUAL ACCESS DRAM
24
Patent #:
7099234
Issue Dt:
08/29/2006
Application #:
10878925
Filing Dt:
06/28/2004
Publication #:
US20050286339
Pub Dt:
12/29/2005
Title:
LOW POWER SLEEP MODE OPERATION TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND INTEGRATED CIRCUIT DEVICES INCORPORATING EMBEDDED DRAM
25
Patent #:
7180363
Issue Dt:
02/20/2007
Application #:
10900505
Filing Dt:
07/28/2004
Publication #:
US20060022742
Pub Dt:
02/02/2006
Title:
POWERGATING METHOD AND APPARATUS
26
Patent #:
7154795
Issue Dt:
12/26/2006
Application #:
10903815
Filing Dt:
07/30/2004
Publication #:
US20060023530
Pub Dt:
02/02/2006
Title:
CLOCK SIGNAL INITIATED PRECHARGE TECHNIQUE FOR ACTIVE MEMORY SUBARRAYS IN DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND OTHER INTEGRATED CIRCUIT DEVICES INCORPORATING EMBEDDED DRAM
27
Patent #:
7151711
Issue Dt:
12/19/2006
Application #:
11064353
Filing Dt:
02/23/2005
Publication #:
US20060187727
Pub Dt:
08/24/2006
Title:
SELF-ADDRESSED SUBARRAY PRECHARGE
28
Patent #:
7372765
Issue Dt:
05/13/2008
Application #:
11198031
Filing Dt:
08/05/2005
Publication #:
US20050270074
Pub Dt:
12/08/2005
Title:
POWER-GATING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICES
29
Patent #:
7586355
Issue Dt:
09/08/2009
Application #:
11776371
Filing Dt:
07/11/2007
Publication #:
US20090015311
Pub Dt:
01/15/2009
Title:
LOW SKEW CLOCK DISTRIBUTION TREE
30
Patent #:
7463054
Issue Dt:
12/09/2008
Application #:
11854422
Filing Dt:
09/12/2007
Title:
DATA BUS CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES
Assignor
1
UNITED MEMORIES INC.
Exec Dt:
01/28/2010
Assignee
1
SONY CORPORATION
1-7-1 KONAN, MINATO-KU
TOKYO, JAPAN 108-0075
Correspondence name and address
DANIEL M. GURFINKEL
120 SOUTH LASALLE STREET, SUITE 1400
CHICAGO, IL 60603

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